Method and apparatus for locking a transmitter oscillator to a reference clock signal in a frequency domain
Methods and apparatuses are provided for locking a transmitter oscillator to a reference clock signal in a frequency domain. The apparatus includes a digital phase-frequency detector. The digital phase-frequency detector includes a mod-M counter, a mod-N counter, and a count evaluation digital circuit. The mod-M counter is designed to count reference clock cycles of a reference clock signal. The mod-N counter is designed to count local clock cycles of a local clock signal. The count evaluation digital circuit is designed to compare the counted reference clock cycles and the local clock cycles with a predefined register setting to generate a control signal as a feedback signal. The control signal is transmitted to the transmitter oscillator through a frequency-locked loop circuit for adjusting the frequency of the transmitter oscillator to be consistent with the reference clock signal.
1. An apparatus, the apparatus comprising a digital phase-frequency detector, the digital phase-frequency detector comprising:
a count evaluation digital circuit;
a mod-M counter associated with a modulus value M, the mod-M counter configured to:
receive a reference clock signal;
count reference clock cycles of the reference clock signal based on the modulus value M; and
generate a reference clock cycle count signal to be transmitted to the count evaluation digital circuit based on the reference clock cycles; and
a mod-N counter associated with a modulus value N, the mod-N counter configured to:
receive a local clock signal associated with a transmitter oscillator;
count local clock cycles of the local clock signal based on the modulus value N; and
generate a local clock cycle count signal to be transmitted to the count evaluation digital circuit based on the local clock cycles,
wherein the count evaluation digital circuit is configured to:
receive the reference clock cycle count signal from the mod-M counter and the local clock cycle count signal from the mod-N counter;
receive a predefined register setting associated with a fixed ratio between the modulus value M and the modulus value N; and
compare the reference clock cycle count signal and the local cycle count signal with the predefined register setting to generate a control signal.
2. The apparatus of claim 1 , wherein the transmitter oscillator comprises a voltage-controlled oscillator (VCO), a number-controlled oscillator (NCO), or a digitally controlled oscillator (DCO).
3. The apparatus of claim 1 , further comprising a multiplexer configured to:
generate a combined reference clock signal based on incoming reference clock signals received from digital channels associated with a first chip comprising the transmitter oscillator or other chips within a transmitter module comprising the first chip and the other chips.
4. The apparatus of claim 3 , wherein the digital phase-frequency detector further comprises a flip-flop digital circuit configured to:
sample the combined reference clock signal based on the local clock signal for generating the reference clock signal to be transmitted to the mod-M counter.
5. The apparatus of claim 3 , further comprising a divider configured to provide the local clock signal to the digital channels associated with the first chip comprising the transmitter oscillator or the other chips.
6. The apparatus of claim 1 , wherein the digital phase-frequency detector further comprises a control logic digital circuit configured to:
receive the reference clock cycle count signal from the mod-M counter;
generate an enable/reset signal based on the reference clock cycle count signal; and
transmit the enable/reset signal to the mod-N counter.
7. The apparatus of claim 6 , wherein the generation of the local clock cycle count signal by the mod-N counter is further based on the enable/reset signal.
8. The apparatus of claim 1 , further comprising a loop filter configured to:
receive the control signal generated by the count evaluation digital circuit of the digital frequency detector; and
transmit the control signal to the transmitter oscillator for adjusting frequency of the local clock signal to be consistent with the reference clock signal.
9. The apparatus of claim 1 , wherein the control signal comprises at least an up signal and a down signal.
10. A method, comprising:
receiving, by a mod-M counter associated with a modulus value M, a reference clock signal;
counting, by the mod-M counter, reference clock cycles of the reference clock signal based on the modulus value M;
generating, by the mod-M counter, a reference clock cycle count signal to be transmitted to a count evaluation digital circuit based on the reference clock cycles;
receiving, by a mod-N counter associated with a modulus value N, a local clock signal associated with a transmitter oscillator;
counting, by the mod-N counter, local clock cycles of the local clock signal based on the modulus value N;
generating, by the mod-N counter, a local clock cycle count signal to be transmitted to the count evaluation digital circuit based on the local clock cycles;
receiving, by the count evaluation digital circuit, the reference clock cycle count signal from the mod-M counter and the local clock cycle count signal from the mod-N counter;
receiving, by the count evaluation digital circuit, a predefined register setting associated with a fixed ratio between the modulus value M and the modulus value N; and
comparing, by the count evaluation digital circuit, the reference clock cycle count signal and the local cycle count signal with the predefined register setting to generate a control signal.
11. The method of claim 10 , wherein the transmitter oscillator comprises a voltage-controlled oscillator (VCO), a number-controlled oscillator (NCO), or a digitally controlled oscillator (DCO).
12. The method of claim 10 , further comprising:
generating, by a multiplexer, a combined reference clock signal based on incoming reference clock signals received from digital channels associated with a first chip comprising the transmitter oscillator or other chips within a transmitter module comprising the first chip and the other chips.
13. The method of claim 12 , further comprising:
sampling, by a flip-flop digital circuit, the combined reference clock signal based on the local clock signal for generating the reference clock signal to be transmitted to the mod-M counter.
14. The method of claim 12 , further comprising:
providing, by a divider, the local clock signal to the digital channels associated with the first chip comprising the transmitter oscillator or the other chips.
15. The method of claim 10 , further comprising:
receiving, by a control logic digital circuit, the reference clock cycle count signal from the mod-M counter;
generating, by the control logic digital circuit, an enable/reset signal based on the reference clock cycle count signal; and
transmitting, by the control logic digital circuit, the enable/reset signal to the mod-N counter.
16. The method of claim 15 , wherein the generation of the local clock cycle count signal by the mod-N counter is further based on the enable/reset signal.
17. The method of claim 10 , further comprising:
receiving, by a loop filter, the control signal generated by the count evaluation digital circuit; and
transmitting, by the loop filter, the control signal to the transmitter oscillator for adjusting a frequency of the local clock signal to be consistent with the reference clock signal.
18. The method of claim 10 , wherein the control signal comprises at least an up signal and a down signal.