SEMICONDUCTOR MEMORY DEVICE

1 . A semiconductor memory device comprising:

a substrate;

a device isolation layer disposed in the substrate defining an active region extending in a first direction;

first conductive lines disposed in the active region and extending in a second direction crossing the first direction;

a second conductive line disposed on the active region between the first conductive lines and extending in a third direction crossing the first direction and the second direction;

a bit line node contact disposed between the active region and the second conductive line;

a landing pad disposed on an edge portion of the active region;

a storage node contact between the landing pad and the edge portion of the active region;

a buried pattern disposed between the bit line node contact and the storage node contact;

a first spacer disposed between a sidewall of the second conductive line and the landing pad;

an air spacer disposed between the first spacer and the landing pad; and

a capping pattern protruding from a sidewall of the landing and disposed on the air spacer,

wherein the capping pattern is spaced apart from the first spacer.

2 . The semiconductor memory device of claim 1 , wherein the capping pattern partially covers an upper portion of the air spacer.

3 . The semiconductor memory device of claim 1 , wherein the capping pattern comprises a barrier pattern and a metal pattern stacked on the edge portion of the active region,

wherein the capping pattern includes the same material as the barrier pattern,

wherein the capping pattern includes a different material with a material of the metal pattern.

4 . The semiconductor memory device of claim 1 , wherein the capping pattern comprises a barrier pattern and a metal pattern stacked disposed on the active region,

wherein the capping pattern includes a different material with a material of the barrier pattern,

wherein the capping pattern includes the same material as the metal pattern.

5 . The semiconductor memory device of claim 1 , further comprising a second spacer disposed between the landing pad and the air spacer below the capping pattern,

wherein the capping pattern is in contact with the second spacer.

6 . The semiconductor memory device of claim 1 , further comprising a second spacer disposed between the landing pad and the air spacer below the capping pattern,

wherein the capping pattern is spaced apart from the second spacer.

7 . The semiconductor memory device of claim 1 , further comprising a second spacer disposed between the landing pad and the air spacer below the capping pattern,

wherein the second spacer is covered a portion of the sidewall of the landing pad.

8 . The semiconductor memory device of claim 1 , further comprising a gap fill layer disposed on the capping pattern,

wherein the gap fill layer covers a portion of the sidewall of the landing pad above the capping pattern and a top surface of the capping pattern.

9 . The semiconductor memory device of claim 1 , further comprising a gap fill layer disposed on the capping pattern,

wherein the gap fill layer covers a top surface of the capping pattern,

wherein the gap fill layer completely covers an upper portion of the air spacer exposed by the capping pattern.

10 . The semiconductor memory device of claim 9 , wherein the gap fill layer is in contact with the first spacer.

11 . The semiconductor memory device of claim 9 , wherein the gap fill layer is spaced apart from the first spacer.

12 . The semiconductor memory device of claim 1 , further comprising a gap fill layer disposed on the capping pattern,

wherein the gap fill layer covers a top surface of the capping pattern,

wherein a level of a lowermost upper surface of the gap fill layer from an upper surface of the substrate is lower than a level of top surface of the capping pattern from the upper surface of the substrate.

13 . The semiconductor memory device of claim 1 , further comprising a gap fill layer disposed on the capping pattern,

wherein the gap fill layer covers a top surface of the capping pattern,

wherein a level of a lowermost upper surface of the gap fill layer from an upper surface of the substrate is higher than a level of top surface of the capping pattern from the upper surface of the substrate.

14 . The semiconductor memory device of claim 1 , further comprising a data storage member disposed on the landing pad.

15 . A semiconductor memory device comprising:

a substrate;

a device isolation layer disposed in the substrate defining an active region extending in a first direction;

first conductive lines disposed in the active region and extending in a second direction crossing the first direction;

a second conductive line disposed on the active region between the first conductive lines and extending in a third direction crossing the first direction and the second direction;

a bit line node contact disposed between the active region and the second conductive line;

a landing pad disposed on an edge portion of the active region;

a storage node contact between the landing pad and the edge portion of the active region;

a buried pattern disposed between the bit line node contact and the storage node contact an air spacer disposed between a sidewall of the second conductive line and the landing pad; and

a capping pattern protruding from a sidewall of the landing pad,

wherein the capping pattern partially covers an upper portion of the air spacer.

16 . The semiconductor memory device of claim 15 , further comprising a gap fill layer on the capping pattern,

wherein the gap fill layer completely covers the upper portion of the air spacer exposed by the capping pattern.

17 . The semiconductor memory device of claim 15 , wherein the capping pattern comprises a barrier pattern and a metal pattern stacked on the edge portion of the active region,

wherein the capping pattern includes the same material as the barrier pattern,

wherein the capping pattern includes a different material with a material of the metal pattern.

18 . The semiconductor memory device of claim 15 , wherein the capping pattern comprises a barrier pattern and a metal pattern stacked on the edge portion of the active region,

wherein the capping pattern includes a different material with a material of the barrier pattern,

wherein the capping pattern includes the same material as the metal pattern.

19 . A semiconductor memory device comprising:

a substrate;

a device isolation layer disposed in the substrate defining an active region extending in a first direction;

first conductive lines disposed in the active region and extending in a second direction crossing the first direction;

a second conductive line disposed on the active region between the first conductive lines and extending in a third direction crossing the first direction and the second direction;

a bit line node contact disposed between the active region and the second conductive line;

a landing pad disposed on an edge portion of the active region;

a storage node contact between the landing pad and the edge portion of the active region;

a buried pattern disposed between the bit line node contact and the storage node contact;

an air spacer disposed between a sidewall of the second conductive line and the landing pad;

a capping pattern protruding from a sidewall of the landing pad; and

a gap fill layer on the capping pattern;

wherein the capping pattern covers a first upper portion of the air spacer,

wherein the gap fill layer covers a second upper portion the air spacer.

20 . The semiconductor memory device of claim 19 , wherein the capping pattern includes the same material as the material of the landing pad,

wherein the gap fill layer includes an insulating material.