Field effect transistor using carbon nanotubes
In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure including carbon nanotubes (CNTs) embedded in a semiconductor layer is formed, a sacrificial gate structure is formed over the fin structure, the semiconductor layer is doped at a source/drain region of the fin structure, an interlayer dielectric (ILD) layer is formed over the doped source/drain region and the sacrificial gate structure, a source/drain opening is formed by patterning the ILD layer, and a source/drain contact layer is formed over the doped source/drain region of the fin structure.
1. A method of forming a gate-all-around field effect transistor (GAA FET), the method comprising:
forming a fin structure including carbon nanotubes (CNTs) embedded in a semiconductor layer;
forming a sacrificial gate structure over the fin structure;
forming a doped source/drain region by doping the semiconductor layer at a source/drain region of the fin structure;
forming an interlayer dielectric (ILD) layer over the doped source/drain region and the sacrificial gate structure;
forming a source/drain opening by patterning the ILD layer; and
forming a source/drain contact layer over the doped source/drain region of the fin structure.
2. The method of claim 1 , wherein the semiconductor layer is crystalline silicon.
3. The method of claim 1 , wherein an impurity concentration in the semiconductor layer after the doping is in a range from 1×10 20 atoms/cm 3 to about 1×10 21 atoms/cm 3 .
4. The method of claim 1 , wherein the semiconductor layer is doped by ion implantation.
5. The method of claim 1 , wherein the doping the semiconductor layer comprises:
forming a doping layer containing impurities over the source/drain region; and
driving the impurities into the source/drain region by a thermal operation.
6. The method of claim 1 , wherein the semiconductor layer is poly crystalline or amorphous.
7. The method of claim 1 , wherein the fin structure is formed by:
(i) disposing a group of CNTs over a substrate;
(ii) forming an epitaxial semiconductor layer to cover the CNTs;
(iii) repeating (i) and (ii) for 2 to 10 times to form a stacked structure; and
(iv) patterning the stacked structure by one or more lithography and etching operations.
8. The method of claim 7 , wherein the epitaxial semiconductor layer is made of a same material as the substrate.
9. The method of claim 7 , wherein a thickness of the epitaxial semiconductor layer is in a range from 5 nm to 15 nm.
10. The method of claim 1 , wherein in forming the source/drain opening, 20% to 80% of a height of the fin structure is exposed in the source/drain opening.
11. A method of forming a gate-all-around field effect transistor (GAA FET), the method comprising:
forming a fin structure, in which carbon nanotubes (CNTs) are embedded in a support material, over a substrate;
forming a sacrificial gate structure over the fin structure;
forming an insulating layer over the sacrificial gate structure and the fin structure;
removing the sacrificial gate structure so that a part of the fin structure is exposed to form an exposed part of the fin structure;
removing the support material from the exposed part of the fin structure so that channel regions of CNTs are exposed to form exposed channel regions of CNTs;
forming a gate structure around the exposed channel regions of CNTs;
forming a source/drain opening in the insulating layer;
removing the support material in the source/drain opening so that source/drain regions of the CNTs are exposed to form exposed CNTs;
forming a semiconductor layer around the exposed CNTs in the source/drain opening; and
forming a source/drain contact layer over the semiconductor layer.
12. The method of claim 11 , wherein after the source/drain opening is formed, a part of the substrate is exposed in the source/drain opening.
13. The method of claim 12 , wherein the semiconductor layer is crystalline silicon epitaxially formed on the exposed substrate.
14. The method of claim 11 , wherein after the source/drain opening is formed, a dielectric layer is disposed between the substrate and a bottom of the source/drain opening so that the substrate is not exposed.
15. The method of claim 14 , wherein the semiconductor layer is poly crystalline or amorphous.
16. The method of claim 11 , wherein an impurity concentration in the semiconductor layer is in a range from 2×10 20 atoms/cm 3 to about 5×10 20 atoms/cm 3 .
17. A method of forming a field effect transistor, the method comprising:
disposing a carbon nanotube (CNT) on a support layer disposed over a substrate;
forming a sacrificial gate structure over the CNT;
forming an insulating layer over the sacrificial gate structure and the CNT;
replacing the sacrificial gate structure with a metal gate structure;
forming exposed CNTs by forming a source/drain opening in the insulating layer;
forming a semiconductor layer around the exposed CNTs in the source/drain opening; and
forming a source/drain contact layer over the semiconductor layer.
18. The method of claim 17 , wherein after the source/drain opening is formed, a part of the substrate is exposed in the source/drain opening.
19. The method of claim 18 , wherein the semiconductor layer is crystalline silicon epitaxially formed on the part of the substrate.
20. The method of claim 18 , wherein after the source/drain opening is formed, an insulating layer is disposed between the substrate and a bottom of the source/drain opening so that the substrate is not exposed.