Integrated circuit devices with parallel power amplifier output paths
An integrated circuit device is provided. In some examples, the integrated circuit device includes a first amplifier path, a second amplifier path coupled in parallel with the first amplifier path, a matching network coupled to the first amplifier path and the second amplifier path, and an antenna coupled to the matching network. In some such examples, the first amplifier path includes a first differential power amplifier coupled to the matching network, and the second amplifier path includes a second differential power amplifier coupled to the matching network. The integrated circuit device may further include a controller coupled to selectively enable the first amplifier path to provide a transmitter output power within a first range and to selectively enable the second amplifier path to provide a transmitter output power within a second range that is different from the first range.
1. An integrated circuit device comprising:
a first differential amplifier path including a first output and a second output;
a second differential amplifier path coupled in parallel with the first differential amplifier path, the second differential amplifier path including a third output and a fourth output;
a balun including a first coil coupled to the first output and the second output;
a matching network coupled to the balun, wherein the matching network includes a switching network; and
an antenna coupled to the matching network;
wherein the third output is coupled to a second coil of the balun; and
wherein the fourth output is coupled to the matching network.
2. The integrated circuit device of claim 1 , wherein:
the first differential amplifier path includes a first differential power amplifier coupled to the balun; and
the second differential amplifier path includes a second differential power amplifier coupled to the matching network and the balun.
3. The integrated circuit device of claim 2 , wherein the second differential amplifier path further includes a third differential power amplifier coupled to a differential input of the second differential power amplifier.
4. The integrated circuit device of claim 1 further comprising a controller coupled to control the first differential amplifier path, the second differential amplifier path, and the switching network of the matching network.
5. The integrated circuit device of claim 4 , wherein the controller is configured to:
selectively enable the first differential amplifier path to provide a transmitter output power within a first range; and
selectively enable the second differential amplifier path to provide a transmitter output power within a second range that is less than the first range.
6. The integrated circuit device of claim 4 , wherein:
the controller is configured to set a state of the switching network based on which of the first differential amplifier path and the second differential amplifier path is selectively enabled.
7. The integrated circuit device of claim 1 further comprising a driver element coupled to provide an input signal to each of the first differential amplifier path and the second differential amplifier path.
8. The integrated circuit device of claim 7 , wherein the second differential amplifier path includes:
a first stage power amplifier coupled to receive the input signal from the driver element and to produce a second signal in response to the input signal; and
a second stage power amplifier coupled to receive the second signal from the first stage power amplifier and to produce a third signal in response to the second signal.
9. The integrated circuit device of claim 8 , wherein:
the matching network includes:
the second coil of the balun;
a first capacitor coupled in parallel with the balun; and
a second capacitor coupled in parallel with the first capacitor.
10. The integrated circuit device of claim 9 , wherein the matching network further includes:
a first switch coupled to the balun;
a second switch coupled to the first capacitor; and
a third switch coupled to the second capacitor.
11. An integrated circuit comprising:
a first differential power amplifier;
a second differential power amplifier coupled in parallel with the first differential power amplifier;
a balun coupled to the first differential power amplifier;
a matching network coupled to the balun, wherein the second differential power amplifier is coupled to the balun and the matching network, wherein the matching network includes a set of switches; and
a controller coupled to control the first differential power amplifier, the second differential power amplifier, and the set of switches, wherein the controller is configured to selectively enable one of the first differential power amplifier and the second differential power amplifier based on a specified output power.
12. The integrated circuit of claim 11 wherein the controller is further configured to control the set of switches based on the specified output power.
13. The integrated circuit of claim 11 , wherein the first differential power amplifier includes a differential set of outputs coupled to the balun.
14. The integrated circuit of claim 13 , wherein the second differential power amplifier includes a first differential output coupled to the balun and a second differential output coupled to the matching network.
15. The integrated circuit of claim 11 , wherein the matching network includes:
a coil of the balun coupled to the second differential power amplifier and coupled in parallel with an antenna;
a first capacitor coupled in parallel with the balun and the antenna; and
a second capacitor coupled in parallel with the balun, the first capacitor, and the antenna.
16. The integrated circuit of claim 15 , wherein the second differential output is coupled to the first capacitor.
17. The integrated circuit of claim 15 , wherein the set of switches includes:
a first switch coupled between the balun and a terminal of the antenna;
a second switch coupled between the first capacitor and the terminal of the antenna; and
a third switch coupled between the second capacitor and the terminal of the antenna.
18. An integrated circuit comprising:
a processing resource; and
a non-transitory computer-readable medium coupled to the processing resource and storing instructions that, when executed by the processing resource, cause the processing resource to:
determine a transmitter output power;
selectively enable one of a first differential amplifier path and a second differential amplifier path based on the determined transmitter output power; and
cause the selected one of the first differential amplifier path and the second differential amplifier path to transmit a signal in accordance with the determined transmitter output power;
wherein the first differential amplifier path is coupled to a balun; and
wherein the second differential amplifier path is coupled to the balun and a matching network that includes a set of switches.
19. The integrated circuit of claim 18 , wherein:
the instructions include further instructions that cause the processing resource to control the set of switches based on the transmitter output power.
20. The integrated circuit of claim 18 , wherein:
the first differential amplifier path includes a first differential power amplifier; and
the second differential amplifier path includes a second differential power amplifier.