IP Library › Granted Patent US 11,562,212
Granted Patent B2
US 11,562,212 · App. 16/565,308 · Granted Jan 24, 2023

Performing XNOR equivalent operations by adjusting column thresholds of a compute-in-memory array

Inventors: Zhongze Wang (San Diego, CA); Edward Teague (San Diego, CA); Max Welling (Bussum, NL)
Assignee: Qualcomm Incorporated
G06N3/0481G06N3/084
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Quick Facts
Patent No.
US 11,562,212
App. No.
16/565,308
Granted
Jan 24, 2023
Kind
B2
Abstract

A method performs XNOR-equivalent operations by adjusting column thresholds of a compute-in-memory array of an artificial neural network. The method includes adjusting an activation threshold generated for each column of the compute-in-memory array based on a function of a weight value and an activation value. The method also includes calculating a conversion bias current reference based on an input value from an input vector to the compute-in-memory array, the compute-in-memory array being programmed with a set of weights. The adjusted activation threshold and the conversion bias current reference are used as a threshold for determining the output values of the compute-in-memory array.

Claims (29)

1. An apparatus comprising:

a compute-in-memory array comprising rows and columns, the compute-in-memory array configured:

to adjust an activation threshold generated for each column of the compute-in- memory array based on a function of a weight value and an activation value; and

to calculate a conversion bias current reference based on an input value from an input vector to the compute-in-memory array, the compute-in-memory array programmed with a set of weight values, in which the adjusted activation threshold and the conversion bias current reference are used as a threshold for determining output values of the compute-in-memory array.

2. The apparatus of claim 1 , further comprising a comparator configured to compare a bit line population count to a sum of the conversion bias current reference and the adjusted activation threshold in order to determine an output of a bit line.

3. The apparatus of claim 1 , in which an artificial neural network including the compute-in-memory array comprises a binary neural network.

4. The apparatus of claim 1 , in which the activation threshold is less than half of a number of rows of the compute-in-memory array, the number of rows corresponding to a size of the input vector.

5. The apparatus of claim 1 , in which the conversion bias current reference is less than half of a number of rows of the compute-in-memory array, the number of rows corresponding to a size of the input vector.

6. A processor-implemented method comprising:

adjusting an activation threshold generated for each column of the compute-in-memory array having rows and columns based on a function of a weight value and an activation value;

calculating a conversion bias current reference based on an input value from an input vector to the compute-in-memory array, the compute-in-memory array being programmed with a set of weight values, in which the adjusted activation threshold and the conversion bias current reference are used as a threshold for determining output values of the compute-in-memory array.

7. The processor-implemented method of claim 6 , further comprising comparing a bit line population count to a sum of the conversion bias current reference and the adjusted activation threshold in order to determine an output of a bit line.

8. The processor-implemented method of claim 6 , in which an artificial neural network including the compute-in-memory array comprises a binary neural network.

9. The processor-implemented method of claim 6 , in which the activation threshold is less than half of a number of rows of the compute-in-memory array, the number of rows corresponding to a size of the input vector.

10. The processor-implemented method of claim 6 , in which the conversion bias current reference is less than half of a number of rows of the compute-in-memory array, the number of rows corresponding to a size of the input vector.

11. A non-transitory computer-readable medium having program code recorded thereon, the program code being executed by a processor and comprising:

program code to adjust an activation threshold generated for each column of a compute-in-memory array having rows and columns based on a function of a weight value and an activation value; and

program code to calculate a conversion bias current reference based on an input value from an input vector to the compute-in-memory array, the compute-in-memory array being programmed with a set of weight values, in which the adjusted activation threshold and the conversion bias current reference are used as a threshold for determining output values of the compute-in-memory array.

12. The non-transitory computer-readable medium of claim 11 , further comprising program code to compare a bit line population count to a sum of the conversion bias current reference and the adjusted activation threshold in order to determine an output of a bit line.

13. The non-transitory computer-readable medium of claim 11 , in which an artificial neural network subject to the adjusting and the calculating comprises a binary neural network.

14. The non-transitory computer-readable medium of claim 11 , in which the activation threshold is less than half of a number of rows of the compute-in-memory array, the number of rows corresponding to a size of the input vector.

15. The non-transitory computer-readable medium of claim 11 , in which the conversion bias current reference is less than half of a number of rows of the compute-in-memory array, the number of rows corresponding to a size of the input vector.

16. An apparatus comprising:

means for adjusting an activation threshold generated for each column of the compute-in- memory array having rows and columns based on a function of a weight value and an activation value; and

means for calculating a conversion bias current reference based on an input value from an input vector to the compute-in-memory array, the compute-in-memory array being programmed with a set of weight values, in which the adjusted activation threshold and the conversion bias current reference are used as a threshold for determining output values of the compute-in-memory array.

17. The apparatus of claim 16 , further comprising means for comparing a bit line population count to a sum of the conversion bias current reference and the adjusted activation threshold in order to determine an output of a bit line.

18. The apparatus of claim 16 , in which an artificial neural network including the compute-in-memory array comprises a binary neural network.

19. The apparatus of claim 16 , in which the activation threshold is less than half of a number of rows of the compute-in-memory array, the number of rows corresponding to a size of the input vector.

20. The apparatus of claim 16 , in which the conversion bias current reference is less than half of a number of rows of the compute-in-memory array, the number of rows corresponding to a size of the input vector.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2019
From: WANG, ZHONGZE; TEAGUE, EDWARD; WELLING, MAX
To: QUALCOMM INCORPORATED
Reel/Frame 051052/0001 →
Continuity (1)
Related Publication 20210073619A1 · Mar 11, 2021