Fabricating field-effect transistors with body contacts between source, gate and drain assemblies
The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly.
1. A method for fabricating a field-effect transistor (FET), the method comprising:
providing a substrate;
implementing a first assembly of source, gate, and drain on a first active region of the substrate;
implementing a second assembly of source, gate, and drain implemented on a second active region of the substrate;
forming a first body contact between the first assembly and the second assembly, the first body contact formed such that application of a voltage on the first body contact influences operation of the first assembly and the second assembly;
forming a first connecting metal extending along a width of the first body contact on a first side; and
forming a second connecting metal extending along a width of the first body contact on a second side opposite the first side.
2. The method of claim 1 wherein the substrate includes a silicon-on-insulator (SOI) substrate.
3. The method of claim 1 wherein the first assembly and the second assembly are dimensioned the same and the first body contact is positioned at the center of the FET.
4. The method of claim 1 further comprising:
implementing a third assembly of source, gate, and drain on a third active region of the substrate; and
forming a second body contact between the second assembly and the third assembly.
5. The method of claim 4 wherein the first assembly and the third assembly are dimensioned the same such that the first body contact and the second body contact are positioned symmetrically about a center line of the FET.
6. The method of claim 5 wherein the second assembly is dimensioned such that it has a width that is equal to the combined widths of the first assembly and the third assembly.
7. The method of claim 1 further comprising forming a finger configuration for the source, the gate, and the drain on each of the first assembly and the second assembly, each finger configuration including a plurality of fingers.
8. The method of claim 7 wherein the finger configuration of each of the first assembly and the second assembly results in source fingers and drain fingers being interleaved with the gate fingers.
9. The method of claim 8 wherein the source fingers and the drain fingers are arranged in alternating rows.
10. The method of claim 9 further comprising electrically connecting a particular source finger of the first assembly to a source finger of the second assembly that is positioned on the same row as the particular source finger of the first assembly.
11. The method of claim 10 further comprising electrically connecting a particular drain finger of the first assembly to a drain finger of the second assembly that is positioned on the same row as the particular drain finger of the first assembly.
12. The method of claim 9 further comprising electrically connecting a particular source finger of the first assembly to a source finger of the second assembly that is offset by one row from the particular source finger of the first assembly.
13. The method of claim 12 further comprising electrically connecting a particular drain finger of the first assembly to a drain finger of the second assembly that is offset by one row from the particular drain finger of the first assembly.
14. The method of claim 1 further comprising:
implementing a first plurality of gate fingers;
electrically coupling the first plurality of gate fingers to the first connecting metal that extends away from the first connecting metal over the first active region;
implementing a second plurality of gate fingers; and
electrically coupling the second plurality of gate fingers to the second connecting metal that extends away from the second connecting metal over the second active region.
15. The method of claim 14 further comprising forming a third connecting metal that electrically couples the first connecting metal and the second connecting metal to electrically connect the first plurality of gate fingers and the second plurality of gate fingers.
16. A method for fabricating a radio-frequency (RF) device, the method comprising:
forming a field-effect transistor (FET) over a substrate layer, the FET including a first assembly of source, gate, and drain on a first active region of the substrate layer, the FET also including a second assembly of source, gate, and drain implemented on a second active region of the substrate layer, the FET also including a first body contact implemented between the first assembly and the second assembly, the first body contact formed such that application of a voltage on the first body contact influences operation of the first assembly and the second assembly, the FET also including a first connecting metal extending along a width of the first body contact on a first side, the FET also including a second connecting metal extending along a width of the first body contact on a second side opposite the first side;
electrically connecting the substrate layer to a substrate node; and
coupling a non-grounding circuit to the substrate node to adjust RF performance of the FET.
17. The method of claim 16 wherein the RF device is a switch.
18. The method of claim 16 wherein the FET further includes a finger configuration for the source, the gate, and the drain on each of the first assembly and the second assembly, each finger configuration including a plurality of fingers.
19. The method of claim 18 wherein the finger configuration of each of the first assembly and the second assembly results in source fingers and drain fingers being interleaved with the gate fingers.
20. A method for fabricating a field-effect transistor (FET), the method comprising:
providing a substrate;
implementing a first assembly of source, gate, and drain on a first active region of the substrate;
implementing a second assembly of source, gate, and drain implemented on a second active region of the substrate;
forming a first body contact between the first assembly and the second assembly, the first body contact formed such that application of a voltage on the first body contact influences operation of the first assembly and the second assembly;
implementing a third assembly of source, gate, and drain on a third active region of the substrate, the second assembly dimensioned such that it has a width that is equal to the combined widths of the first assembly and the third assembly; and
forming a second body contact between the second assembly and the third assembly, the first assembly and the third assembly being dimensioned the same such that the first body contact and the second body contact are positioned symmetrically about a center line of the FET.