3D IC Decoupling capacitor structure and method for manufacturing the same

1. A method for manufacturing a semiconductor structure, comprising:

providing a base layer;

forming a photoresist layer over the base layer, the photoresist layer having an opening;

blanket disposing a first conductive layer over the photoresist layer;

blanket disposing an insulation layer over the conductive layer;

etching a portion of the insulation layer to expose a portion of the first conductive layer outside the opening;

disposing a second conductive layer over the insulation layer and the exposed first conductive layer;

planarizing the second conductive layer until the photoresist layer is exposed; and

removing the photoresist layer, wherein the first conductive layer, the insulation layer and the second conductive layer form a metal-insulator-metal (MIM) capacitor.

2. The method of claim 1 , further comprising disposing a device die over the base layer.

3. The method of claim 1 , further comprising forming a molding layer over the base layer.

4. The method of claim 3 , further comprising performing a planarization process to remove excess portions of the molding layer to expose the MIM capacitor.

5. The method of claim 4 , further comprising removing at least a top portion of the first conductive layer and a top portion of the second conductive layer.

6. The method of claim 5 , further comprising forming a redistribution layer (RDL) over the MIM capacitor.

7. The method of claim 1 , wherein the insulation layer includes high-k dielectric material.

8. The method of claim 7 , wherein the insulation layer includes silicon nitride, silicon carbide, low-temperature silicon dioxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), low-temperature titanium dioxide (TiO 2 ), zirconium dioxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO x ), Hafnium silicate (HfSiO x ), zirconium titanate (ZrTiO x ), tantalum oxide (TaO x ), strontium titanate (SrTiO 3 ), barium titanate (BaTiO3), barium strontium titanate (BaSrTiO 3 ), lead zirconate titanate (PbZrTiO 3 ), or a laminated layer of ZrO 2 —Al 2 O 3 —ZrO 2 .

9. A method for manufacturing a semiconductor structure, comprising:

providing a polymer base layer;

forming a redistribution layer (RDL) over the polymer base layer;

forming a photoresist layer having an opening passing through the photoresist layer over the RDL;

forming a metal-insulator-metal (MIM) capacitor vertically passing through the photoresist layer, the MIM capacitor including a first electrode, an insulation layer and a second electrode, wherein an outer sidewall and an outer bottom surface of the first electrode is lined with the insulation layer, and an outer sidewall and an outer bottom surface of the insulation layer is lined with the second electrode;

performing a CMP upon the MIM capacitor and the photoresist layer; and

removing the photoresist layer.

10. The method of claim 9 , further comprising disposing a device die over the polymer base layer.

11. The method of claim 9 , further comprising forming a molding layer over the base layer.

12. The method of claim 9 , further comprising removing at least a top portion of the first conductive layer and a top portion of the second conductive layer.

13. The method of claim 11 , further comprising forming a patterned polymer layer having openings overlying the molding layer and the MIM capacitor.

14. The method of claim 9 , wherein the insulation layer includes high-k dielectric material.

15. The method of claim 9 , wherein the insulation layer includes silicon nitride, silicon carbide, low-temperature silicon dioxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), low-temperature titanium dioxide (TiO 2 ), zirconium dioxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO x ), Hafnium silicate (HfSiO x ), zirconium titanate (ZrTiO x ), tantalum oxide (TaO x ), strontium titanate (SrTiO 3 ), barium titanate (BaTiO3), barium strontium titanate (BaSrTiO 3 ), lead zirconate titanate (PbZrTiO 3 ), or a laminated layer of ZrO 2 —Al 2 O 3 —ZrO 2 .

16. A method for manufacturing a semiconductor structure, comprising:

providing a polymer base layer;

forming a first redistribution layer (RDL) over the polymer base layer;

forming a photoresist layer having an opening passing through the photoresist layer over the first RDL;

blanket disposing a first conductive layer over the photoresist layer and the first RDL;

blanket disposing an insulation layer over the conductive layer;

etching a portion of the insulation layer to expose a portion of the first conductive layer outside the opening;

disposing a second conductive layer over the insulation layer and the exposed first conductive layer; and

planarizing the second conductive layer until the photoresist layer is exposed.

17. The method of claim 16 , further comprising:

removing a top portion of the first electrode and a top portion of the second electrode to allow the insulation layer to protrude upward from a top surface of the first electrode and a top surface of the second electrode.

18. The method of claim 16 , further comprising disposing a device die over the polymer base layer.

19. The method of claim 16 , further comprising forming a molding layer over the polymer base layer.

20. The method of claim 16 , further comprising forming a second RDL over the second conductive layer.