COMPUTING DEVICE, SIMULATION SUPPORT DEVICE, AND NON-TRANSITORY COMPUTER READABLE MEDIUM
According to one embodiment, the computing device includes a modeling processing unit configured to model characteristics of selected cell transistor and to define a non-selected cell transistor as a parasitic resistance component of the selected cell transistor. The computing device further includes a computation processing unit configured to use as a parameter a distance between both ends of an active region of the selected cell transistor, and further to store threshold characteristics of the selected cell transistor present in the memory string as a parameter, and to obtain electrical characteristics of the selected cell transistor. The computing device is used for a circuit simulation of a semiconductor memory device including memory string of a plurality of cell transistors connected to one another in series in a channel direction.
1 . A computing device used for a circuit simulation of a semiconductor memory device including memory string of a plurality of cell transistors connected to one another in series in a channel direction, the computing device comprising:
a modeling processing unit configured to model characteristics of selected cell transistor which is selected and to define a non-selected cell transistor which is not selected as a parasitic resistance component of the selected cell transistor; and
a computation processing unit configured to use as a parameter a distance between both ends of an active region of the selected cell transistor, and further to store threshold characteristics of the selected cell transistor present in the memory string as a parameter, and to obtain electrical characteristics of the selected cell transistor.
2 . The computing device according to claim 1 , wherein
the modeling processing unit is configured to approximate the selected cell transistor present in the memory string to the one transistor by using the non-selected cell transistor as the parasitic resistance component of the selected cell transistor, and to define by a string length of the memory string a gate length when being approximated.
3 . The computing device according to claim 2 , wherein
the modeling processing unit is configured to model the parasitic resistance component by being regarded as a correction to the gate length.
4 . The computing device according to claim 1 , wherein
the parameter comprises an operation sequence of the non-selected cell transistor.
5 . The computing device according to claim 4 , wherein
the operation sequence of the non-selected cell transistor comprises a writing state of the non-selected cell transistor.
6 . The computing device according to claim 1 , wherein
the parameter comprises a channel length modulation at a source side and a channel length modulation at a drain side.
7 . A simulation support device used for a circuit simulation of a semiconductor memory device including memory string of a plurality of cell transistors connected to one another in series in a channel direction, the simulation support device comprising:
a modeling processing unit configured to model characteristics of selected cell transistor which is selected and to define a non-selected cell transistor which is not selected as a parasitic resistance component of the selected cell transistor; and
a computation processing unit configured to use as a parameter a distance between both ends of an active region of the selected cell transistor, and further to store threshold characteristics of the selected cell transistor present in the memory string as a parameter, and to obtain electrical characteristics of the selected cell transistor
8 . The simulation support device according to claim 7 further comprising
a circuit simulation unit configured to execute the circuit simulation using the obtained electrical characteristics.
9 . The simulation support device according to claim 7 , wherein
the modeling processing unit is configured to approximate the selected cell transistor present in the memory string to the one transistor by using the non-selected cell transistor as the parasitic resistance component of the selected cell transistor, and to define by a string length of the memory string a gate length when being approximated.
10 . The simulation support device according to claim 9 , wherein
the modeling processing unit is configured to model the parasitic resistance component by being regarded as a correction to the gate length.
11 . The simulation support device according to claim 7 , wherein
the parameter comprises an operation sequence of the non-selected cell transistor.
12 . The simulation support device according to claim 11 , wherein
the operation sequence of the non-selected cell transistor comprises a writing state of the non-selected cell transistor.
13 . The simulation support device according to claim 7 , wherein
the parameter comprises a channel length modulation at a source side and a channel length modulation at a drain side.
14 . A non-transitory computer readable medium in which a computer program is stored, the computer program being executed by a computer used for a circuit simulation of a semiconductor memory device including memory string of a plurality of cell transistors connected to one another in series in a channel direction, the computer program comprising:
modelling characteristics of selected cell transistor which is selected and defining a non-selected cell transistor which is not selected as a parasitic resistance component of the selected cell transistor; and
using as a parameter a distance between both ends of an active region of the selected cell transistor, and further storing threshold characteristics of the selected cell transistor present in the memory string as a parameter, and obtaining electrical characteristics of the selected cell transistor.
15 . The non-transitory computer readable medium in which the computer program is stored according to claim 14 , wherein
approximating the selected cell transistor present in the memory string to the one transistor by using the non-selected cell transistor as the parasitic resistance component of the selected cell transistor, and defining by a string length of the memory string a gate length when being approximated.
16 . The non-transitory computer readable medium in which the computer program is stored according to claim 15 , wherein
modelling the parasitic resistance component by being regarded as a correction to the gate length.
17 . The non-transitory computer readable medium in which the computer program is stored according to claim 16 , wherein
the parameter comprises an operation sequence of the non-selected cell transistor.
18 . The non-transitory computer readable medium in which the computer program is stored according to claim 17 , wherein
the operation sequence of the non-selected cell transistor comprises a writing state of the non-selected cell transistor.
19 . The non-transitory computer readable medium in which the computer program is stored according to claim 14 , wherein
the parameter comprises a channel length modulation at a source side and a channel length modulation at a drain side.