Convergence among concurrently executing threads
Convergence of threads executing common code sections is facilitated using instructions inserted at strategic locations in computer code sections. The inserted instructions enable the threads in a warp or other group to cooperate with a thread scheduler to promote thread convergence.
1. A system comprising:
a code profiler configured to insert instructions into a code segment to:
predict an eventual arrival of a thread executing the code segment at an execution barrier in the code segment;
confirm the thread reached the execution barrier;
cancel the predicted arrival of the thread at the execution barrier in a branch of the code segment that will not encounter the execution barrier; and
a thread scheduler configured to:
execute in parallel multiple threads comprising the code segment, each of the multiple threads comprising the instructions inserted by the code profiler; and
suspend execution of threads arriving at the execution barrier while more of the multiple threads are predicted to arrive at the execution barrier.
2. The system of claim 1 , wherein at least one instruction predicting the eventual arrival of the thread at the execution barrier comprises an instruction to join the execution barrier.
3. The system of claim 1 , the code profiler further configured to insert one or more instructions into the code segment to rejoin the execution barrier after the thread scheduler resumes execution of the thread after the execution barrier.
4. The system of claim 1 , the thread scheduler further configured to:
resume execution of the threads suspended at the execution barrier on condition that no more threads are predicted to arrive at the execution barrier.
5. The system of claim 1 , wherein the execution barrier is indicated by a code marker.
6. The system of claim 1 , further comprising the code profiler configuring a range in the code segment in which the prediction of eventual arrival of the thread applies.
7. The system of claim 1 , further comprising:
the code profiler configured to insert one or more instructions into the code segment to configure a threshold value; and
the thread scheduler configured to resume execution of the threads suspended at the execution barrier on condition that the threads that have arrived at the execution barrier satisfy the threshold value.
8. The system of claim 1 , the code profiler comprising:
logic to detect a conflict in a live range of two or more execution barriers, wherein one of the execution barriers is located at a post-dominator of two or more divergent branches of the code segment; and
logic to eliminate the execution barrier at the post-dominator in response to detecting the conflict.
9. The system of claim 1 , the code profiler comprising:
logic to detect a conflict in a live range of two or more execution barriers, wherein one of the execution barriers is located at a post-dominator of two or more divergent branches of the code segment; and
logic to insert one or more instructions into the code segment to cause the thread to cancel, upon reaching one of the two or more conflicting execution barriers, predicted arrival at other ones of the two or more conflicting execution barriers.
10. A method for promoting thread convergence comprising:
defining and inserting a convergence point of an execution barrier in a common section of code executed b a branch of the code;
predicting that a plurality of threads will arrive at the convergence point to execute the common section of the code;
canceling the predicted arrival of a first one or more of the threads at the convergence point in the branch of the code that will not execute to the convergence point; and
delaying execution of a second one or more of the threads at the convergence point until a number of the threads that have not canceled their predicted arrival at the convergence point arrive at the convergence point or cancel theft arrival at the convergence point.
11. The method of claim 10 , wherein the execution of the second one or more of the threads is delayed at the convergence point until all of the threads that have not canceled their predicted arrival at the convergence point arrive at the convergence point or cancel their arrival at the convergence point.
12. The method of claim 10 , wherein the execution of the second one or more of the threads is delayed at the convergence point until a configured threshold level of the threads that have not canceled their predicted arrival at the convergence point arrive at the convergence point or cancel their arrival at the convergence point.
13. The method of claim 10 , further comprising:
marking a code segment of the threads for which prediction of arrival at the convergence point is valid.
14. An apparatus comprising:
one or more processors;
a memory comprising instructions that when executed by the one or more processors result in:
analyzing program code and determining a common code segment to execute in parallel as a plurality of threads, and a divergent code segment;
identifying synchronization point of the plurality of threads;
inserting, into the common code segment an instruction to set a convergence barrier based on the synchronization point;
inserting, into the common code segment, an instruction to join the convergence barrier;
inserting, into time divergent code segment of the threads, an instruction to cancel the join to the convergence barrier, the instruction to cancel the join to the convergence barrier being independent from other instruction to join a different convergence barrier; and
executing the program code with the inserted instructions to promote thread convergence by cooperating with a thread scheduler.
15. The apparatus of claim 14 , the convergence barrier located in a function called from a branch of the common code segment.
16. The apparatus of claim 14 , the convergence barrier located in a variable iteration count loop of the threads.
17. The apparatus of claim 14 , wherein the instructions, when executed by the processor, further result in:
inserting, into the threads at a point following the convergence barrier in an execution flow, at least one instruction to rejoin the convergence barrier.
18. The apparatus of claim 14 , wherein the instructions, when executed by the processor, further result in:
deconfliction of convergence barriers for non-identical overlapping ranges of the threads.
19. The apparatus of claim 14 , further comprising: the thread scheduler configured to delay execution of those threads within the threads that reach the convergence barrier until a number of remaining threads within the threads that have not canceled their join to the convergence barrier arrive at the convergence barrier or cancel their arrival at the convergence barrier.