IP Library Granted Patent US 11,416,355
Granted Patent B2
US 11,416,355 · App. 16/568,165 · Granted Aug 16, 2022

Relay system

Inventor: Hiroyuki Eguchi (Kanagawa, JP)
Assignee: FUJIFILM Business Innovation Corp.
G06F11/2023G06F11/0703G06F11/0751G06F11/3442G06F11/0733G06F2201/85
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Quick Facts
Patent No.
US 11,416,355
App. No.
16/568,165
Granted
Aug 16, 2022
Kind
B2
Abstract

A relay system includes a detector that detects occurrence of failure related to a processor that reads and processes requests from a memory, a monitor that monitors statuses of the requests stored in the memory and gives an instruction to increase or reduce a computational resource depending on the statuses of the requests stored in the memory, and a controller that performs control in response to detection of the failure by the detector so that a status of the memory is set to a state in which the monitor determines that addition of the computational resource is unnecessary.

Claims (23)

1. A relay system, comprising:

a detector that detects occurrence of failure related to a processor that reads and processes requests from a memory;

a monitor that monitors statuses of the requests stored in the memory and gives an instruction to increase or reduce a computational resource depending on the statuses of the requests stored in the memory; and

a controller that performs control in response to detection of the failure by the detector so that a status of the requests are set to a state in which the monitor determines that addition of the computational resource is unnecessary,

wherein the controller performs control so that a status of a request that is being processed in association with the processor related to the detected failure is set to a state in which the processor is not able to acquire the request that is being processed from the memory,

wherein when the detector has detected that the failure no longer occurs, the controller changes the status of the request held in the memory from the state in which the processor is not able to acquire the request from the memory to a state in which the processor is able to acquire the request from the memory.

2. The relay system according to claim 1 , wherein the controller performs control so that a status of a request that is stored in the memory and is waiting for execution of the processor in which the failure has been detected is set to a state in which the request is not acquirable from the memory.

3. The relay system according to claim 1 , wherein the controller performs control so that a status of a request that is stored in the memory and is waiting for execution of the processor in which the failure has been detected is set to a state in which the request is not acquirable from the memory.

4. The relay system according to claim 1 , wherein the controller performs control in response to the detection of the failure so that the number of requests stored in the memory appears not to exceed a predetermined value.

5. The relay system according to claim 1 , wherein, when the failure has been detected in the processor that processes a request before the request is stored in the memory, the controller performs control so that the status of the request generated after the detection of the failure and stored in the memory is set to a state in which the processor is not able to acquire the request from the memory.

6. The relay system according to claim 1 , wherein, when the failure has been detected in the processor that processes a request before the request is stored in the memory, the controller performs control so that the status of the request generated after the detection of the failure and stored in the memory is set to a state in which the processor is not able to acquire the request from the memory.

7. The relay system according to claim 2 , wherein, when the failure has been detected in the processor that processes a request before the request is stored in the memory, the controller performs control so that the status of the request generated after the detection of the failure and stored in the memory is set to a state in which the processor is not able to acquire the request from the memory.

8. The relay system according to claim 3 , wherein, when the failure has been detected in the processor that processes a request before the request is stored in the memory, the controller performs control so that the status of the request generated after the detection of the failure and stored in the memory is set to a state in which the processor is not able to acquire the request from the memory.

9. The relay system according to claim 1 , wherein, when the failure has been detected in the processor that processes the requests, the controller discards a request generated after the detection of the failure without writing the request in the memory.

10. The relay system according to claim 1 , wherein, when the failure has been detected in the processor that processes the requests, the controller discards a request generated after the detection of the failure without writing the request in the memory.

11. The relay system according to claim 2 , wherein, when the failure has been detected in the processor that processes the requests, the controller discards a request generated after the detection of the failure without writing the request in the memory.

12. The relay system according to claim 3 , wherein, when the failure has been detected in the processor that processes the requests, the controller discards a request generated after the detection of the failure without writing the request in the memory.

13. A relay system, comprising:

detection means for detecting occurrence of failure related to a processor that reads and processes requests from a memory;

monitoring means for monitoring statuses of the requests stored in the memory and giving an instruction to increase or reduce a computational resource depending on the statuses of the requests stored in the memory; and

control means for performing control in response to detection of the failure by the detection means so that a status of the requests are set to a state in which the monitoring means determines that addition of the computational resource is unnecessary,

wherein the control means performs control so that a status of a request that is being processed in association with the processor related to the detected failure is set to a state in which the processor is not able to acquire the request that is being processed from the memory,

wherein when the detection means has detected that the failure no longer occurs, the control means changes the status of the request held in the memory from the state in which the processor is not able to acquire the request from the memory to a state in which the processor is able to acquire the request from the memory.

Assignments (2)
CHANGE OF NAME Recorded May 13, 2021
From: FUJI XEROX CO., LTD.
To: FUJIFILM BUSINESS INNOVATION CORP.
Reel/Frame 056223/0007 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2019
From: EGUCHI, HIROYUKI
To: FUJI XEROX CO., LTD.
Reel/Frame 050479/0527 →
Priority Claims (1)
JP JP2018-176618 · Sep 20, 2018 · national
Continuity (1)
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