Just in time data placement in NAND flash
A memory system includes a memory array and a memory controller. The memory array includes a plurality of memory dies communicatively coupled via a plurality of memory channels, each memory channel communicatively coupled to a subset of the plurality of memory dies. The memory controller includes a command scheduler configured to determine an operator status of each memory die of the memory array, determine, based on the operator status of each of the memory dies, an order in which to output commands to the memory dies, update a mapping table based on the determined order in which to output the commands to the memory dies of the memory array, and output the commands to the memory dies of the memory array in the determined order in the mapping table.
1. A memory system comprising:
a memory array including:
a plurality of memory dies communicatively coupled via a plurality of memory channels to a memory controller, each memory channel communicatively coupled to a subset of the plurality of memory dies; and
the memory controller including a command scheduler configured to:
determine an operator status of each memory die of the memory array;
determine, based on the operator status of each of the memory dies, an order in which to output a plurality of commands to the memory dies;
update a mapping table based on the determined order in which to output the plurality of commands to the memory dies of the memory array; and
output the plurality of commands to the memory dies of the memory array in the determined order in the mapping table.
2. The memory system of claim 1 , wherein the memory controller further comprises status indicators storing the operator status of each of the memory dies of the memory array.
3. The memory system of claim 2 , wherein the command scheduler is configured to receive the status indicators and determine the operator status of each memory die of the memory array based on the received status indicators.
4. The memory system of claim 1 , wherein the command scheduler is configured to update the mapping table before outputting the plurality of commands to the memory dies of the memory array.
5. The memory system of claim 1 , wherein the command scheduler is configured to output the plurality of commands to the memory dies of the memory array before updating the mapping table.
6. The memory system of claim 1 , wherein the memory controller further comprises a host interface configured to receive commands from a host.
7. A memory system comprising:
a memory array including:
a plurality of memory dies communicatively coupled via a plurality of memory channels to a memory controller, each memory channel communicatively coupled to a subset of the plurality of memory dies; and
the memory controller comprising a command scheduler configured to:
determine an operator status of each memory die of the memory array;
determine, based on the operator status of each of the memory dies, an order in which to output a plurality of commands to a group of dies of the memory array that is available to receive a strip of data;
update a mapping table based on the determined order in which to output the plurality of commands to the memory dies of the memory array; and
output the plurality of commands to the memory dies of the memory array in the determined order in the mapping table.
8. The memory system of claim 7 , wherein the memory controller further comprises status indicators storing the operator status of each of the memory dies of the memory array.
9. The memory system of claim 8 , wherein the command scheduler is configured to receive the status indicators and determine the operator status of each memory die of the memory array based on the received status indicators.
10. The memory system of claim 7 , wherein the command scheduler is configured to update the mapping table before outputting the plurality of commands to the memory dies of the memory array.
11. The memory system of claim 7 , wherein the command scheduler is configured to output the plurality of commands to the memory dies of the memory array before updating the mapping table.
12. The memory system of claim 7 , wherein the memory controller further comprises a host interface configured to receive commands from a host.
13. A method of scheduling a distribution of commands to memory dies, the method comprising:
determining an operator status of each of a plurality of memory dies in a memory array, wherein the plurality of memory dies are communicatively coupled via a plurality of memory channels to a memory controller, each memory channel communicatively coupled to a subset of the plurality of memory dies;
determining, by the memory controller, based on the operator status of each of the memory dies of the memory array, an order in which to output a plurality of commands to the memory dies of the memory array;
updating, by the memory controller, a mapping table based on the determined order in which to output the plurality of commands to the memory dies of the memory array; and
outputting, by the memory controller, the plurality of commands to the memory dies of the memory array in the determined order in the mapping table.
14. The method of claim 13 , further comprising storing, by the memory controller, the operator status of each of the memory dies of the memory array in status indicators.
15. The method of claim 14 , determining, by the memory controller, the operator status of each memory die of the memory array based on the status indicators.
16. The method of claim 13 , wherein updating the mapping table occurs before outputting the plurality of commands to the memory dies of the memory array.
17. The method of claim 13 , wherein outputting the plurality of commands to memory dies of the memory array occurs before updating the mapping table.