Dielet design techniques
Various implementations described herein are directed to an integrated circuit (IC) having a design that is severable into multiple sub-circuits having input-output (IO) ports. The integrated circuit (IC) may include multiple physical electrical connections that are adapted to electrically interconnect the IO ports of the multiple sub-circuits to operate as the IC, and the IO ports have three-dimensional (3D) geometric position information associated therewith.
1. A device, comprising:
an integrated circuit (IC) having a design that is severable into multiple sub-circuits having input-output (IO) ports, wherein each of the sub-circuits corresponds to a respective dielet; and
multiple physical electrical connections that are adapted to electrically interconnect the IO ports of the multiple sub-circuits to operate as the IC,
wherein the IO ports comprise inter-dielet ports having embedded three-dimensional (3D) geometric position information, and wherein the inter-dielet ports are configured to facilitate integration between the dielets of one or more semiconductor dies.
2. The device of claim 1 , wherein the 3D geometric position information includes x-y-z coordinates in 3D space.
3. The device of claim 1 , wherein the multiple physical electrical connections have the 3D geometric position information associated therewith.
4. The device of claim 1 , wherein the IC has gate structures, and wherein the gate structures have the 3D geometric position information associated therewith.
5. The device of claim 1 , wherein:
the IC comprises multiple dies including a first die and a second die of the one or more semiconductor dies, wherein the second die is physically separate from the first die,
one or more sub-circuits of the multiple sub-circuits of the IC are disposed on the first die, and
one or more other sub-circuits of the multiple sub-circuits of the IC are disposed on the second die.
6. The device of claim 5 , wherein the 10 ports facilitate integration of the multiple sub-circuits disposed on the first die and on the second die.
7. The device of claim 5 , wherein the IC has multiple tiers, and wherein the first die and the second die are on different tiers of the multiple tiers.
8. The device of claim 1 , wherein the multiple physical electrical connections include multiple sub-sets of separate conductive paths that electrically interconnect the multiple sub-circuits to operate as the IC.
9. The device of claim 1 , wherein the IC has multiple tiers, and wherein the multiple sub-circuits are disposed in one or more tiers of the multiple tiers.
10. The device of claim 1 , wherein the design or a portion thereof is described in a unified design database associated with the IC.
11. A method, comprising:
sub-dividing a design of an integrated circuit (IC) into multiple sub-circuits having input-output (IO) ports, wherein each of the sub-circuits corresponds to a respective dielet; and
coupling the IO ports of the multiple sub-circuits with electrical interconnections so as to cause the multiple sub-circuits to operate as the design,
wherein the IO ports comprise inter-dielet ports having embedded three-dimensional (3D) geometric position information, and wherein the inter-dielet ports are configured to facilitate integration between the dielets of one or more semiconductor dies.
12. The method of claim 11 , wherein the 3D geometric position information includes x-y-z coordinates in 3D space.
13. The method of claim 11 , wherein the IC has multiple tiers, and wherein the multiple sub-circuits are disposed in one or more tiers of the multiple tiers.
14. The method of claim 11 , wherein the design or a portion thereof is described in a unified design database associated with the IC.
15. A method, comprising:
sub-dividing a design of an integrated circuit (IC) into multiple sub-circuits having input-output (IO) ports; and
coupling the IO ports of the multiple sub-circuits with electrical interconnections so as to cause the multiple sub-circuits to operate as the design,
wherein the electrical interconnections have embedded three-dimensional (3D) geometric position information.
16. The method of claim 15 , wherein the IC has multiple tiers, and wherein the multiple sub-circuits are disposed in one or more tiers of the multiple tiers.
17. The method of claim 15 , wherein the 3D geometric position information includes x-y-z coordinates in 3D space, and wherein the design or a portion thereof is described in a unified design database associated with the IC.
18. A method, comprising:
sub-dividing a design of an integrated circuit (IC) into multiple sub-circuits having input-output (IO) ports; and
coupling the IO ports of the multiple sub-circuits with electrical interconnections so as to cause the multiple sub-circuits to operate as the design,
wherein the IC has gate structures associated with the IO ports, and wherein the gate structures have embedded three-dimensional (3D) geometric position information.
19. The method of claim 18 , wherein the IC has multiple tiers, and wherein the multiple sub-circuits are disposed in one or more tiers of the multiple tiers.
20. The method of claim 18 , wherein the 3D geometric position information includes x-y-z coordinates in 3D space, and wherein the design or a portion thereof is described in a unified design database associated with the IC.