Semiconductor device with multiple independent gates
Semiconductor device with multiple independent gates. A gate-controlled semiconductor device includes a first plurality of cells of the semiconductor device configured to be controlled by a primary gate, and a second plurality of cells of the semiconductor device configured to be controlled by an auxiliary gate. The primary gate is electrically isolated from the auxiliary gate, and sources and drains of the semiconductor device are electrically coupled in parallel. The first and second pluralities of cells may be substantially identical in structure.
1. A gate-controlled semiconductor device comprising:
a first plurality of cells of said semiconductor device configured to be controlled by a primary gate;
a second plurality of cells of said semiconductor device configured to be controlled by an auxiliary gate,
wherein said primary gate is electrically isolated from said auxiliary gate; and
wherein sources and drains of said semiconductor device are electrically coupled in parallel,
wherein said primary gate is not directly connected to said sources or said drains, and wherein said auxiliary gate is not directly connected to said sources or said drains.
2. The semiconductor device of claim 1 wherein said first and second pluralities of cells are substantially identical in structure.
3. The semiconductor device of claim 1 comprising a channel region comprising gallium nitride (GaN).
4. The semiconductor device of claim 1 wherein an effective resistance of said second plurality of cells is characterized as in a range of 50-200 times an effective resistance of said first plurality of cells.
5. The semiconductor device of claim 1 wherein said second plurality of cells are configured to have a threshold voltage that is different from a threshold voltage of said first plurality of cells.
6. The semiconductor device of claim 1 further comprising a Zener diode coupled between said auxiliary gate and said drains.
7. The semiconductor device of claim 6 wherein a nominal voltage of said Zener diode is in a range of 10-15% below a rated voltage of said first plurality of cells.
8. The semiconductor device of claim 1 further comprising a clamping circuit coupled between said auxiliary gate and said drains, wherein a nominal clamping voltage of said clamping circuit is below an avalanche breakdown voltage of said first plurality of cells.
9. A gate-controlled semiconductor device comprising:
a source terminal;
a drain terminal;
a primary gate terminal configured to control current from said drain terminal to said source terminal in a first fraction of channel area of said semiconductor device; and
an auxiliary gate terminal configured to control current from said drain terminal to said source terminal in a second fraction of channel area of said semiconductor device,
wherein said primary gate terminal is not directly connected to said source terminal or to said drain terminal, and wherein said auxiliary gate terminal is not directly connected to said source terminal or to said drain terminal.
10. The semiconductor device of claim 9 further comprising a channel region comprising gallium nitride (GaN).
11. The semiconductor device of claim 9 wherein said auxiliary gate terminal is electrically coupled to said drain terminal on a die of said semiconductor device.
12. The semiconductor device of claim 9 wherein said auxiliary gate terminal is electrically coupled to said source terminal via an explicit resistance on a die of said semiconductor device.
13. A gate-controlled semiconductor device comprising:
a plurality of primary cells, comprising:
primary source, primary drain, and primary channel regions;
a primary gate electrode coupled to a primary gate terminal of said semiconductor device;
a plurality of auxiliary cells, comprising:
auxiliary source, auxiliary drain, and auxiliary channel regions;
an auxiliary gate electrode coupled to an auxiliary gate terminal of said semiconductor device,
wherein said primary source and said primary drain are coupled in parallel with said auxiliary source and said auxiliary drain forming a common source and a common drain, and
wherein said primary gate terminal and said auxiliary gate terminal are electrically isolated from one another and electrically isolated from said common source and said common drain.
14. The semiconductor device of claim 13 wherein an effective resistance of all of said auxiliary channel regions is in a range of 90-100 times an effective resistance of all of said primary channel regions.
15. The semiconductor device of claim 13 wherein said auxiliary cells are evenly and regularly distributed among said primary cells.
16. The semiconductor device of claim 13 further comprising a Zener diode coupled between said auxiliary gate terminal and said common drain on the same die of said semiconductor device.
17. The semiconductor device of claim 13 further comprising an explicit resistance coupled between said auxiliary gate terminal and said common source on the same die of said semiconductor device.
18. The semiconductor device of claim 13 wherein said auxiliary gate terminal is coupled to an external package terminal.