High bandwidth memory system

1. An apparatus comprising:

a memory;

a data bus configured to transfer data from a processor to a high-bandwidth memory (HBM); and

a controller that receives a data write request from the processor, the controller:

determining data of the data write request comprises sparse data;

storing, based on the data of the data write request comprising sparse data, an entry in the memory, wherein the entry comprises metadata of the data of the data write request;

generating, based on the data of the data write request comprising sparse data, an indication that the data bus is available for an operation by the processor; and

communicating the indication to the processor.

2. The apparatus of claim 1 , wherein:

sparse data comprises a percentage of data values of the data write request equal to zero; and

the percentage of data values equal to zero is based on a data granularity.

3. The apparatus of claim 1 , wherein the entry is a first entry, the metadata is first metadata, and, based on the data of the data write request comprising a data-value similarity being an amount of similarity based on a size of data granularity, the controller further stores a second entry in the memory, wherein the second entry comprises second metadata of data of the data write request.

4. The apparatus of claim 1 , wherein the controller further receives a data read request from the processor for a read access to the HBM, and

wherein the controller further determines an address corresponding to the data read request is stored as an entry in the memory.

5. The apparatus of claim 4 , wherein the controller further performs a sideband access, a parallel memory lookup, and an HBM lookup.

6. The apparatus of claim 3 , wherein the second entry comprises information relating to the data-value similarity of the data write request, and

wherein the controller further compresses the entry to reduce a data width.

7. The apparatus of claim 1 ,

wherein the controller further compresses the metadata as a series of blocks in the memory.

8. A system, comprising:

a processor;

a high-bandwidth memory (HBM);

a data bus configured to transfer data from the processor to the HBM; and

a controller that includes a memory, the controller:

receiving a data write request from the processor,

determining data of the data write request comprises sparse data,

storing, based on data of the data write request comprising sparse data, an entry in the memory of the controller, wherein the entry comprises metadata of the data of the data write request,

generating, based on the data write request comprising sparse data, an indication that the data bus is available for an operation by the processor, and

communicating the indication to the processor.

9. The system of claim 8 , wherein:

the sparse data comprises a percentage of data values of data of the data write request equal to zero; and

the percentage of data values equal to zero of sparse data is based on a data granularity.

10. The system of claim 8 , wherein the entry is a first entry, the metadata is first metadata, the controller further:

stores, based on data of the data write request further comprising data-value similarity, a second entry in the memory of the controller, wherein the second entry comprises second metadata of the data of the data write request, and

generates, based on the data write request further comprising data-value similarity, the indication that a data bus is available for the operation, and

wherein data of the data write request comprises an amount of spatial value locality, and

wherein the amount of spatial value locality of the data-value similarity is based on a data granularity.

11. The system of claim 8 , wherein the controller further receives a data read request from the processor for a read access to the HBM, and

wherein the controller further determines an address corresponding to the data read request is stored as an entry in the memory.

12. The system of claim 11 , wherein the controller further performs a sideband access, a parallel memory lookup, and an HBM lookup.

13. The system of claim 8 , wherein the first entry further comprises information relating to data-value similarity of the data of the data write request, and

wherein the controller further compresses the entry to reduce a data width.

14. The system of claim 8 ,

wherein the controller further compresses the metadata as a series of blocks in the memory.

15. A method, comprising:

receiving, at a controller of a high-bandwidth memory (HBM), a data write request from a processor, wherein the HBM comprises a data bus configured to transfer data from the processor to the HBM;

determining, by the controller, data of the data write request comprises sparse data;

storing, by the controller, based on data of the data write request comprising sparse data, an entry in a memory of the controller, wherein the entry comprises metadata of data of the data write request;

generating, by the controller, based on data of the data write request comprising sparse data, an indication that data bus is available for an operation by the processor; and

communicating the indication to the processor.

16. The method of claim 15 , wherein the entry is a first entry, the metadata is first metadata, and sparse data comprises a percentage of data values of data of the data write request equal to zero, wherein the data of the data write request comprises an amount of spatial value locality, and the indication is based on data of the data write comprising the amount of spatial value locality,

the method further comprising:

generating, by the controller, based on the data write request further comprising the amount of spatial value locality, the indication that the data bus is available;

storing, by the controller, based on data of the data write request comprising a data-value similar, a second entry in the memory of the controller, wherein the second entry comprises second metadata of data of the data write request; and

generating, by the controller, based on the data of the data write request comprising data-value similarity, an indication that the data bus is available for an operation.

17. The method of claim 15 , wherein the data of the data write request comprises a percentage of data values of data of the data write request equal to zero, and the indication is based on the data of the data write request comprising the percentage of data values of data of the data write request equal to zero,

the method further comprising:

generating, by the controller, based on the data write request further comprising sparse data, the indication that a data bus is available for the operation,

wherein the percentage of data values equal to zero of sparse data is based on a data granularity.

18. The method of claim 15 , further comprising:

receiving a data read request from the processor for a read access to the HBM;

determining that an address corresponding to the data read request is stored as an entry in the memory; and

performing a sideband access, a parallel memory lookup, and an HBM lookup based on the address corresponding to the data read request being stored as an entry in the memory.

19. The method of claim 16 , wherein the second entry comprises information relating to the data-value similarity of data of the data write request,

the method further comprising compressing the second entry to reduce a data width.

20. The method claim 15 ,

further comprising compressing the metadata as a series of blocks in the memory.