Integrated circuit design using fuzzy machine learning

1. A method, comprising:

receiving a functional integrated circuit design;

generating a plurality of place and route (PnR) layouts based on the received functional integrated circuit design and first and second integrated circuit floorplans, the first integrated circuit floorplan including a first blockage having a same shape and size as a first blockage in the second integrated circuit floorplan;

applying one or more rules to analyze attributes associated with each of the generated PnR layouts, wherein the rules include variables having truth values that may be any real number between 0 and 1 inclusive; and

determining a PnR layout of the plurality of PnR layouts having an area utilization complying with the one or more rules.

2. The method of claim 1 , wherein the rules are fuzzy logic rules, and wherein applying the rules to analyze the generated PnR layouts includes:

for each of the plurality of PnR layouts:

applying one or design analyses to the PnR layout to generate the attributes associated with the PnR layout;

fuzzifying the attributes;

generating an output based on the one or more fuzzy logic rules; and

defuzzifying the output.

3. The method of claim 2 , further comprising:

classifying and ranking the plurality of PnR layouts based on at least the area utilization.

4. The method of claim 2 , further comprising locating a second blockage at a same location in each of the first and second integrated circuit floorplans, wherein the second blockage in each of the first and second integrated circuit floorplans is different from another blockage in the first and second integrated circuit floorplans.

5. The method of claim 4 , wherein a size of each second blockage is different from a size of another blockage.

6. The method of claim 2 , further comprising:

modifying the one or more fuzzy logic rules based on the determined PnR layout of the plurality of PnR layouts having an area utilization complying with the one or more fuzzy logic rules.

7. The method of claim 2 , further comprising:

modifying fuzzification criteria, utilized to fuzzify the attributes, based on the determined PnR layout of the plurality of PnR layouts having an area utilization complying with the one or more fuzzy logic rules.

8. The method of claim 1 , further comprising:

generating a knowledge database based on the plurality of PnR layouts having an area utilization complying with the one or more fuzzy logic rules.

9. The method of claim 1 , further comprising:

manufacturing a system on chip based on the PnR layout of the plurality of PnR layouts having an area utilization complying with the one or more fuzzy logic rules.

10. A system, comprising:

a processor;

a database accessible by the processor storing fuzzy logic rules;

computer-readable media accessible by the processor, the computer-readable media storing instructions that when executed by the processor implement a method, comprising:

receiving a functional integrated circuit design,

generating a plurality of place and route (PnR) layouts based on the received functional integrated circuit design and one or more integrated circuit floorplans,

applying one or more of the fuzzy logic rules stored in the database to analyze attributes associated with each of the generated PnR layouts,

determining a PnR layout of the plurality of PnR layouts having an area utilization complying with the one or more fuzzy logic rules,

classifying and ranking the plurality of PnR layouts based on at least the area utilization selecting a portion of the classified and ranked plurality of PnR layouts based on at least the area utilization, and

modifying at least one of fuzzification criteria, one or more logic rules, and/or one or more floorplans.

11. The system of claim 10 , wherein the one or more floorplans includes a first floorplan and a second floorplan different from the first floorplan, the first floorplan including a blockage having a same shape and size as a blockage in the second floorplan.

12. The system of claim 10 , wherein the method of applying the fuzzy logic rules to analyze the generated PnR layouts includes:

for each of the plurality of PnR layouts:

applying one or design analyses to the PnR layout to generate the attributes associated with the PnR layout;

fuzzifying the attributes;

generating an output based on the one or more fuzzy logic rules; and

defuzzifying the output.

13. The system of claim 12 , wherein the database is stored in the computer readable media.

14. The system of claim 12 , wherein the method further comprises:

applying one or more of the fuzzy logic rules to analyze attributes associated with each of the classified and ranked plurality of PnR layouts; and

determining a second PnR layout of the plurality of PnR layouts having an area utilization complying with the applied one or more fuzzy logic rules.

15. The system of claim 10 , wherein the method further comprises:

systematically altering a blockage at a same location in each of the one or more integrated circuit floorplans.

16. The system of claim 10 , wherein the method further comprises:

modifying the one or more of the fuzzy logic rules based on the determined PnR layout of the plurality of PnR layouts having an area utilization complying with the one or more fuzzy logic rules.

17. The system of claim 10 , wherein the method further comprises:

modifying fuzzification criteria, utilized to fuzzify the attributes, based on the determined PnR layout of the plurality of PnR layouts having an area utilization complying with the one or more fuzzy logic rules.

18. The system of claim 10 , wherein the method further comprises:

generating a knowledge database based on the plurality of PnR layouts having an area utilization complying with the one or more fuzzy logic rules.

19. A computer-readable medium including one or more instructions, which when executed by a processor, cause the processor to:

receive a functional integrated circuit design;

generate a plurality of place and route (PnR) layouts based on the received functional integrated circuit design and one or more integrated circuit floorplans; and

for each of the generated plurality of PnR layouts:

apply one or design analyses to the PnR layout to generate attributes associated with the PnR layout,

fuzzify the attributes,

generate an output based on the one or more fuzzy logic rules; and

defuzzify the output, and

determine a PnR layout of the plurality of PnR layouts having an area utilization complying with the one or more fuzzy logic rules.

20. The computer-readable medium of claim 19 , wherein the one or more instructions cause the processor to:

select a portion of the plurality of PnR layouts based on at least the area utilization;

modify at least one of fuzzification criteria, one or more logic rules, and/or one or more floorplans;

apply one or more different fuzzy logic rules to analyze attributes associated with each of the plurality of PnR layouts; and

determine a second PnR layout of the plurality of PnR layouts having an area utilization complying with the applied one or more fuzzy logic rules.