Low noise differential amplifier
In one general aspect, an amplifier can include an input amplifier circuit configured to receive a bias current and receive, as an input, a signal pair connected differentially to the input amplifier circuit, the input amplifier circuit configured to output a differential output signal pair based on the received differential input signal pair, a feedback amplifier circuit configured to receive an average of the differential output signal pair and configured to provide a bias setting output for controlling the bias current, and an output buffer circuit configured to buffer the differential output signal pair, the buffering resulting in a buffered differential output signal pair capable of driving a resistive load.
1. A pre-amplifier comprising:
a first stage including:
a feedback amplifier circuit configured to control an output voltage swing of an output differential signal pair in relation to a bias current by providing a constant output voltage signal gain for the output differential signal pair;
an input amplifier circuit configured to receive the bias current and configured to receive, as an input, an input differential signal pair connected differentially to the input amplifier circuit through a blocking capacitor, the input amplifier circuit configured to output the output differential signal pair based on the input differential signal pair and the bias current, the input amplifier circuit including a transistor and resistor block controllable to switch output load resistors to the input amplifier circuit; and
a second stage including:
a buffer circuit configured to amplify an output signal of the output differential signal pair to generate a buffered output signal configured to drive a resistive load included in a gain module.
2. The pre-amplifier of claim 1 , further comprising a DC bias module configured to set a high pass filter frequency for the pre-amplifier.
3. The pre-amplifier of claim 2 , wherein the DC bias module includes a plurality of resistors and a plurality of metal oxide semiconductor (MOS) transistors controlling the plurality of resistors for setting a DC bias for the input differential signal pair.
4. The pre-amplifier of claim 2 , wherein the high pass filter frequency is further based on a value of the blocking capacitor.
5. The pre-amplifier of claim 2 , wherein the feedback amplifier circuit is a common mode feedback circuit, the feedback amplifier circuit has an input voltage that is a second common mode reference voltage and the DC bias module has an input voltage that is a first common mode reference voltage.
6. The pre-amplifier of claim 5 , wherein a value of the first common mode reference voltage and a value of the second common mode reference voltage are set in order to control an input common mode range for the pre-amplifier.
7. The pre-amplifier of claim 1 , wherein the transistor and resistor block includes a plurality of metal oxide semiconductor (MOS) transistors to control a switching of output load resistors to the input amplifier circuit, the output load resistors have a value determining a magnitude of current for consumption by the input amplifier circuit, and the magnitude of current consumed determines a level of noise in the pre-amplifier.
8. The pre-amplifier of claim 7 , wherein the pre-amplifier has a common mode gain that is determined based on a matching of the output load resistors.
9. The pre-amplifier of claim 1 , wherein the feedback amplifier circuit has an input that is a combination of a first output signal voltage of the output differential signal pair and a second output signal voltage of the output differential signal pair.
10. The pre-amplifier of claim 9 , further comprising an input bias current module configured to generate the bias current and provide the bias current to the input amplifier circuit, the feedback amplifier circuit having an output controlling the generating of the bias current by the input bias current module.
11. An amplifier comprising:
a feedback amplifier circuit configured to control an output voltage swing of an output differential signal pair in relation to a bias current by providing a constant output voltage signal gain for the output differential signal pair;
an input amplifier circuit configured to receive the bias current and configured to receive, as an input, an input differential signal pair connected differentially to the input amplifier circuit through a pair of capacitors, the input amplifier circuit configured to output the output differential signal pair based on the input differential signal pair and the bias current;
a DC bias module coupled between the pair of capacitors and the input amplifier circuit and configured to control a high pass filter frequency of the amplifier; and
an output buffer including a first buffer circuit and a second buffer circuit, the first buffer circuit configured to amplify a first output signal of the output differential signal pair to generate a first buffered output signal configured to drive a first resistive load, the second buffer circuit configured to amplify a second output signal of the output differential signal pair to generate a second buffered output signal configured to drive a second resistive load.
12. The amplifier of claim 11 , wherein the DC bias module includes a plurality of resistors and a plurality of metal oxide semiconductor (MOS) transistors controlling the plurality of resistors for setting a DC bias for the input differential signal pair.
13. The amplifier of claim 11 , wherein the high pass filter frequency is further based on a value of the pair of capacitors.
14. The amplifier of claim 11 , wherein the feedback amplifier circuit is a common mode feedback circuit, the feedback amplifier circuit has an input voltage that is a second common mode reference voltage and the DC bias module has an input voltage that is a first common mode reference voltage.
15. The amplifier of claim 14 , wherein a value of the first common mode reference voltage and a value of the second common mode reference voltage are set in order to control an input common mode range for the amplifier.
16. The amplifier of claim 11 , wherein the amplifier is a pre-amplifier having a first stage that includes the feedback amplifier circuit and the input amplifier circuit, and having a second stage that includes the output buffer, and the first resistive load and the second resistive load are included in a gain module.
17. The amplifier of claim 11 , wherein the input amplifier circuit includes a transistor and resistor block controllable to switch output load resistors to the input amplifier circuit, the transistor and resistor block including a plurality of metal oxide semiconductor (MOS) transistors configured to control a switching of output load resistors to the input amplifier circuit, the output load resistors have a value determining a magnitude of current for consumption by the input amplifier circuit, and the magnitude of current consumed determines a level of noise in the amplifier.
18. The amplifier of claim 17 , wherein the amplifier has a common mode gain that is determined based on a matching of the output load resistors.
19. The amplifier of claim 11 , wherein the feedback amplifier circuit has an input that is a combination of a first output signal voltage of the output differential signal pair and a second output signal voltage of the output differential signal pair.
20. The amplifier of claim 11 , further comprising an input bias current module configured to generate the bias current and provide the bias current to the input amplifier circuit, the feedback amplifier circuit having an output controlling the generating of the bias current by the input bias current module.