System and method for construction cost estimation for non-computer aided design (CAD) files
A computing device has a processor. A display is coupled to the processor. A user interface is coupled to the processor for entering data into the computing device. A memory is coupled to the processor, the memory storing program instructions that when executed by the processor, causes the processor to: display a floorplan of a blueprint file, wherein the blueprint file is a non-CAD file; select a scale factor for the floorplan; mark and label at least one electrical panel; generate wire routes from selected points on the floorplan to a desired electrical panel of the at least one electrical panel, wherein generating wire routes comprises generating a straight line path from one of the selected points to the desired electrical panel when a direct route is selected; and generate a cost for each of the wire routes generated.
1. A computing device comprising:
a processor;
a display coupled to the processor;
a user interface coupled to the processor for entering data into the computing device; and
a memory coupled to the processor, the memory storing program instructions that when executed by the processor, causes the processor to:
display a floorplan of a blueprint file, wherein the blueprint file is a non-CAD file;
select a scale factor for the floorplan;
mark and labeling at least one electrical panel;
generate wire routes from selected points on the floorplan to a desired electrical panel of the at least one electrical panel, wherein generating wire routes comprises generating a straight-line path from one of the selected points to the desired electrical panel when a direct route is selected; and
generate a cost for each of the wire routes generated.
2. The computing device of claim 1 , wherein generating wire routes comprises generating a multi-line path from one of the selected points to the desired electrical panel when an orthogonal route is selected, wherein adjacent lines of the multi-line path are orthogonal to one another.
3. The computing device of claim 2 , wherein each line of the multi-line path runs one of a horizontal direction or a vertical direction.
4. The computing device of claim 1 , wherein the memory causes the processor to mark at least one non-wiring area on the floorplan.
5. The computing device of claim 4 , wherein generate wire routes comprises generating a first section wherein the first section is a first section straight line from one of the selected points to the at least one non-wiring area and generating a second section, wherein the second section is a second section multi-line path to the desired electrical panel.
6. The computing device of claim 5 , wherein the second section multi-line path is a plurality of lines around the at least one non-wiring area, wherein adjacent lines of the plurality of lines are orthogonal to one another when the direct route is selected.
7. The computing device of claim 1 , wherein the memory causes the processor to mark at least one cable route on the floorplan.
8. The computing device of claim 7 , wherein generate wire routes comprises generating a first section wherein the first section is a first line from one of the selected points to the at least one cable route and generating a second section, wherein the second section is a second section multi-line path following the at least one cable route when an orthogonal route is selected.
9. The computing device of claim 8 , wherein the first line is one of a vertical line or a horizontal line from one of the selected points to the at least one cable route.
10. The computing device of claim 1 , wherein the memory causes the processor to generate an estimated material takeoff window, the estimated material takeoff window displaying calculated estimated costs for each of the wire routes.
11. The computing device of claim 10 , wherein the estimated material takeoff window displays a material used in calculating the estimated costs for each of the wire routes.
12. The computing device of claim 1 , wherein the memory causes the processor to generate an estimated material takeoff window, the estimated material takeoff window displaying calculated estimated costs for selected wire routes.
13. A computing device comprising:
a processor;
a display coupled to the processor;
a user interface coupled to the processor for entering data into the computing device; and
a memory coupled to the processor, the memory storing program instructions that when executed by the processor, causes the processor to:
display a floorplan of a blueprint file, wherein the blueprint file is a non-CAD file;
select a scale factor for the floorplan;
mark and labeling at least one electrical panel;
generate wire routes from selected points on the floorplan to a desired electrical panel of the at least one electrical panel, wherein generating wire routes comprises:
generating a straight-line path from one of the selected points to the desired electrical panel when a direct route is selected;
generating a multi-line path from one of the selected points to the desired electrical panel when an orthogonal route is selected, wherein adjacent lines of the multi-line path are orthogonal to one another;
generate a cost for each of the wire routes generated; and
generate an estimated material takeoff window, the estimated material takeoff window displaying calculated estimated costs for selected wire routes generated.
14. The computing device of claim 13 , wherein each line of the multi-line path runs one of a horizontal direction or a vertical direction.
15. The computing device of claim 13 , wherein the memory causes the processor to mark at least one non-wiring area on the floorplan.
16. The computing device of claim 15 , wherein generate wire routes comprises generating a first section wherein the first section is a first section straight line from one of the selected points to the at least one non-wiring area and generating a second section, wherein the second section is a second section multi-line path to the desired electrical panel.
17. The computing device of claim 16 , wherein the second section multi-line path is a plurality of lines around the at least one non-wiring area, wherein adjacent lines of the plurality of lines are orthogonal to one another when the direct route is selected.
18. The computing device of claim 13 , wherein the memory causes the processor to mark at least one cable route on the floorplan.
19. The computing device of claim 18 , wherein generate wire routes comprises generating a first section wherein the first section is a first line from one of the selected points to the at least one cable route and generating a second section, wherein the second section is a second section multi-line path following the at least one cable route when an orthogonal route is selected.
20. The computing device of claim 19 , wherein the first line is one of a vertical line or a horizontal line from one of the selected points to the at least one cable route.