Decoupling capacitor and method of making the same

1. A semiconductor device comprising:

a substrate;

a plurality of source/drain (S/D) regions in the substrate, wherein each of the plurality of S/D regions includes a first dopant having a first dopant type, and the each of the plurality of S/D regions are electrically coupled together;

a gate stack over the substrate; and

a channel region in the substrate, wherein the channel region is below the gate stack and between adjacent S/D regions of the plurality of S/D regions, the channel region includes a second dopant having the first dopant type, and a concentration of the second dopant in the channel region is less than a concentration of the first dopant in each of the plurality of S/D regions; and

an n-well in the substrate, wherein the n-well extends under the channel region and the adjacent S/D regions of the plurality of S/D regions, and the first dopant type is p-type.

2. The semiconductor device of claim 1 , wherein the first dopant is a same material as the second dopant.

3. The semiconductor device of claim 1 , wherein the first dopant is a different material from the second dopant.

4. The semiconductor device of claim 1 , wherein the n-well is electrically coupled to each of the plurality of S/D regions.

5. The semiconductor device of claim 1 , further comprising a lightly doped drain (LDD) region between the channel region and the n-well, wherein the LDD region comprises an n-type dopant.

6. The semiconductor device of claim 1 , wherein the concentration of the second dopant in the channel region is less than half of the concentration of the first dopant in each of the plurality of S/D regions.

7. A semiconductor device comprising:

a substrate, wherein the substrate is p-doped;

a plurality of source/drain (S/D) regions in the substrate, wherein the plurality of S/D regions comprises a first S/D region and a second S/D region, each of the first S/D region and the second S/D region includes a first dopant having a first dopant type, and the first S/D region is electrically coupled to the second S/D region;

a gate stack over the substrate; and

a channel region in the substrate, wherein the channel region is below the gate stack and between the first S/D region and the second S/D region, the channel region includes a second dopant having the first dopant type, a concentration of the second dopant in the channel region is less than a concentration of the first dopant in each of the first S/D region and the second S/D region, and an entirety of the substrate below the channel region is free of dopants of the first dopant type.

8. The semiconductor device of claim 7 , wherein the concentration of the first dopant is at least twice the concentration of the second dopant.

9. A semiconductor device comprising:

a substrate;

a plurality of source/drain (S/D) regions in the substrate, wherein each of the plurality of S/D regions includes a first dopant having a first dopant type, and the each of the plurality of S/D regions are permanently electrically connected together;

a gate stack over the substrate;

a channel region in the substrate, wherein the channel region is below the gate stack and between adjacent S/D regions of the plurality of S/D regions, the channel region includes a second dopant having the first dopant type, and a first concentration of the second dopant in the channel region is less than a second concentration of the first dopant in each of the plurality of S/D regions; and

an n-well in the substrate, wherein the n-well extends under the channel region and the adjacent S/D regions of the plurality of S/D regions, and the first dopant type is p-type.

10. The semiconductor device of claim 9 , wherein a first S/D region of the plurality of S/D regions has the second concentration at least twice the first concentration.

11. The semiconductor device of claim 9 , wherein a second S/D region of the plurality of S/D regions has the second concentration at least twice the first concentration.

12. The semiconductor device of claim 9 , wherein the n-well directly contacts the channel region and each of the plurality of S/D regions.

13. The semiconductor device of claim 9 , further comprising a lightly doped drain (LDD) region, wherein the LDD is between the n-well and an entirety of a first S/D region of the plurality of S/D regions.

14. The semiconductor device of claim 1 , further comprising a terminal, wherein each of the plurality of S/D regions are permanently electrically connected to the terminal.

15. The semiconductor device of claim of claim 7 , further comprising a terminal, wherein each of the plurality of S/D regions are permanently electrically connected to the terminal.

16. The semiconductor device of claim 1 , wherein the n-well directly contacts a sidewall of each of the plurality of S/D regions.

17. The semiconductor device of claim 1 , wherein a depth of the channel in the substrate is less than a depth of each of the plurality of S/D regions in the substrate.

18. The semiconductor device of claim 7 , wherein the p-doped substrate directly contacts a sidewall of the first S/D region.

19. The semiconductor device of claim 9 , wherein the n-well extends across an entirety of a distance between the plurality of S/D regions.

20. The semiconductor device of claim 19 , wherein an entirety of the substrate below the n-well is free of n-type dopants.