Tracking and communication of direct/indirect source dependencies of producer instructions executed in a processor to source dependent consumer instructions to facilitate processor optimizations

1. A processor, comprising:

an instruction processing circuit comprising one or more instruction pipelines and configured to fetch a plurality of instructions from a memory into an instruction pipeline among the one or more instruction pipelines;

an instruction dependency tracking table circuit comprising a plurality of source entries each associated with a respective source, and each configured to store a source dependency indicator indicating a producer instruction of the associated source; and

an instruction dependency tracking circuit configured to:

receive an instruction from an instruction pipeline among the one or more instruction pipelines;

determine if the received instruction comprises a source as a target operand; and

in response to determining the received instruction comprises the source as the target operand:

store an instruction identifier of the received instruction in an updated source dependency indicator in a source entry associated with the source in the instruction dependency tracking table circuit; and

communicate the updated source dependency indicators stored in the plurality of source entries to at least one processing circuit in the instruction processing circuit configured to process an instruction having a source dependency in the updated source dependency indicators.

2. The processor of claim 1 , further comprising:

a physical register file comprising a plurality of physical registers; and

a rename map table circuit comprising the instruction dependency tracking table circuit, the rename map table circuit comprising:

the plurality of source entries and further configured to store at least one address pointer pointing to an address of a physical register among the plurality of physical registers in the physical register file; and

wherein:

the instruction processing circuit is configured to map a source of a producer instruction among the fetched plurality of instructions to a source entry in the rename map table circuit mapped to the physical register among the plurality of physical registers in the physical register file.

3. The processor of claim 1 , wherein each of the plurality of source entries in the instruction dependency tracking table circuit are configured to store the source dependency indicator comprising a source dependency bit vector comprising a plurality of bits, where each bit is configured to indicate a designated producer instruction of the associated source.

4. The processor of claim 1 , wherein the instruction dependency tracking circuit is configured to communicate the updated source dependency indicators to a reservation station circuit as a processing circuit among the at least one processing circuit.

5. The processor of claim 1 , wherein the instruction processing circuit further comprises a scheduler circuit comprising a processing circuit among the at least one processing circuit, scheduler circuit comprising:

a source dependency broadcast bus configured to receive a source dependency indicator communicated by the instruction dependency tracking circuit; and

a reservation station circuit, comprising:

a plurality of reservation entries each configured to store a received instruction from an instruction pipeline among the one or more instruction pipelines to be executed; and

at least one pick circuit configured to identify instructions in the plurality of reservation entries to be issued in an issue lane circuit to be executed; and

a plurality of source readiness circuits each comprising a source entry, each coupled to the at least one pick circuit, and each assigned to a respective source, each of the plurality of source readiness circuits configured to:

receive the updated source dependency indicator associated with its respective source on the source dependency broadcast bus; and

replace an existing source dependency indicator with the received updated source dependency indicator in its source entry.

6. The processor of claim 5 , wherein the plurality of source readiness circuits are each further configured to:

determine if a new producer instruction is identified in the updated source dependency indicator; and

in response to determining the new producer instruction is identified in the updated source dependency indicator, cause an instruction in a reservation entry among the plurality of reservation entries having the source of the source dependency indicator to be replayed.

7. The processor of claim 6 , wherein the plurality of source readiness circuits are each further configured to:

determine if a new producer instruction is identified in the updated source dependency indicator; and

in response to determining the new producer instruction is identified in the updated source dependency indicator, instruct the at least one pick circuit to unpick an instruction in a reservation entry among the plurality of reservation entries having the source of the source dependency indicator.

8. The processor of claim 5 , wherein the plurality of source readiness circuits are each further configured to:

determine if a new producer instruction is identified in the updated source dependency indicator; and

in response to determining the new producer instruction is identified in the updated source dependency indicator, instruct the at least one pick circuit to unpick an instruction in a reservation entry among the plurality of reservation entries having the source of the source dependency indicator.

9. The processor of claim 5 , wherein:

the plurality of source readiness circuits are each further configured to:

determine if the received updated source dependency indicator does not indicate any producer instructions; and

in response to determining the received updated source dependency indicator does not indicate any producer instructions, generate a register free indicator indicating a free state for its associated source; and

the scheduler circuit further comprises a free register circuit configured to receive the register free indicator from the respective plurality of source readiness circuits, and generate an entry free indicator indicating a free state to the plurality of reservation entries indicating that instructions having source dependencies can be freed.

10. The processor of claim 1 ,

further comprising an influencer tracking table circuit comprising:

a plurality of influencer instruction entries each associated with a producer instruction among the fetched plurality of instructions;

each influencer instruction entry among the plurality of influencer instruction entries comprising a source indicator indicating a source location of an instruction having a source dependency with an influencer instruction associated with the plurality of influencer instruction entries;

the instruction dependency tracking circuit further configured to:

in response to determining the received instruction comprises the source:

index an influencer instruction entry in the influencer tracking table circuit based on the updated source dependency indicator; and

update the source indicator in the indexed influencer instruction entry in the influencer tracking table circuit with a source location of an instruction having a source dependency with an influencer instruction associated with the indexed influencer instruction entry.

11. The processor of claim 10 , wherein the instruction dependency tracking circuit is further configured to, in response to determining the received instruction comprises the source:

communicate the updated source dependency indicators stored in the plurality of source entries to a processing circuit among the at least one processing circuit, identified by the source locations in source indicators in an indexed influencer instruction entry in the influencer tracking table circuit associated with the respective updated source dependency indicator.

12. The processor of claim 11 , wherein the instruction processing circuit further comprises a scheduler circuit comprising a processing circuit among the at least one processing circuit, scheduler circuit comprising:

a plurality of source dependency lines each configured to receive an updated source dependency indicator associated with the source communicated by the instruction dependency tracking circuit; and

a reservation station circuit, comprising:

a plurality of reservation entries each configured to store a received instruction from an instruction pipeline among the one or more instruction pipelines to be executed;

at least one pick circuit configured to identify instructions in the plurality of reservation entries to be issued in an issue lane circuit to be executed; and

a plurality of source readiness circuits each coupled to the at least one pick circuit, and each assigned to a respective source, each of the plurality of source readiness circuits configured to:

receive an updated source dependency indicator associated with its respective source on a source dependency line among the plurality of source dependency lines associated with its respective source; and

replace an existing source dependency indicator with the received updated source dependency indicator in its source entry.

13. The processor of claim 12 , wherein the plurality of source readiness circuits are each further configured to:

determine if a new producer instruction is identified in the updated source dependency indicator; and

in response to determining if the new producer instruction is identified in the updated source dependency indicator, cause an instruction in a reservation entry among the plurality of reservation entries having the source of the source dependency indicator to be replayed.

14. The processor of claim 13 , wherein the plurality of source readiness circuits are each further configured to:

determine if a new producer instruction is identified in the updated source dependency indicator; and

in response to determining the new producer instruction is identified in the updated source dependency indicator, instruct the at least one pick circuit to unpick an instruction in a reservation entry among the plurality of reservation entries having the source of the source dependency indicator.

15. The processor of claim 12 , wherein the plurality of source readiness circuits are each further configured to:

determine if a new producer instruction is identified in the updated source dependency indicator; and

in response to determining the new producer instruction is identified in the updated source dependency indicator, instruct the at least one pick circuit to unpick an instruction in a reservation entry among the plurality of reservation entries having the source of the source dependency indicator.

16. The processor of claim 12 , wherein:

the plurality of source readiness circuits are each further configured to:

determine if the received updated source dependency indicator does not indicate any producer instructions;

in response to determining the received updated source dependency indicator does not indicate any producer instructions, generate a register free indicator indicating a free state for its associated source; and

the reservation station circuit further comprising a free register circuit configured to receive the register free indicator from the respective plurality of source readiness circuits, and generate an entry free indicator indicating a free state to the plurality of reservation entries indicating that instructions having source dependencies can be freed.

17. A method of tracking source dependencies of producer instructions in a processor, comprising:

receiving an instruction from an instruction pipeline among one or more instruction pipelines in an instruction processing circuit;

determining if the received instruction comprises a source as a target operand; and

in response to determining the received instruction comprises the source as the target operand:

storing an instruction identifier of the received instruction in an updated source dependency indicator indicating a producer instruction of an associated source in a source entry among a plurality of source entries in an instruction dependency tracking table circuit; and

communicating the updated source dependency indicators stored in the plurality of source entries to at least one processing circuit in the instruction processing circuit configured to process an instruction having a source dependency in the updated source dependency indicators.

18. The method of claim 17 ,

wherein communicating the updated source dependency indicators further comprises broadcasting the updated source dependency indicators on a source dependency broadcast bus coupled to a scheduler circuit in the instruction processing circuit; and

further comprising:

receiving an instruction from an instruction pipeline among the one or more instruction pipelines to be executed;

identifying instructions in a plurality of reservation entries to be issued in an issue lane circuit to be executed;

receiving the updated source dependency indicator associated with its respective source on the source dependency broadcast bus; and

replacing an existing source dependency indicator with the received updated source dependency indicator in its source entry.

19. The method of claim 18 , further comprising:

determining if a new producer instruction is identified in the updated source dependency indicator; and

causing an instruction in a reservation entry among the plurality of reservation entries having the source of a source dependency indicator to be replayed, in response to determining the new producer instruction is identified in the updated source dependency indicator.

20. The method of claim 18 , further comprising, in response to determining the received instruction comprises the source:

indexing an influencer instruction entry in an influencer tracking table circuit based on the updated source dependency indicator, the influencer tracking table circuit comprising:

a plurality of influencer instruction entries each associated with a producer instruction among a fetched plurality of instructions; and

each influencer instruction entry among the plurality of influencer instruction entries comprising a source indicator indicating a source location of an instruction having a source dependency with an influencer instruction associated with the plurality of influencer instruction entries; and

updating the source indicator in the indexed influencer instruction entry in the influencer tracking table circuit with a source location of an instruction having a source dependency with the influencer instruction associated with the indexed influencer instruction entry.