Image sensor with shallow trench edge doping

1. A method of forming an integrated chip, comprising:

doping a substrate to form a first well region having a first doping type;

selectively etching an upper surface of the substrate to define a trench extending into the first well region;

filling the trench with one or more dielectric materials;

implanting the substrate to form a first photodiode region within the substrate, wherein the first photodiode region is separated from the trench by the first well region;

removing a first part of the one or more dielectric materials from within the trench to expose a sidewall of the substrate that defines the trench and that is proximate to the first photodiode region; and

forming a doped epitaxial material having the first doping type along the sidewall of the substrate.

2. The method of claim 1 , wherein the doped epitaxial material continuously extends from within the trench to directly over the first photodiode region.

3. The method of claim 1 , wherein the doped epitaxial material has an upper surface that is over the upper surface of the substrate.

4. The method of claim 1 , wherein the doped epitaxial material has a first doping concentration that is larger than a second doping concentration of the first well region.

5. The method of claim 1 , further comprising:

doping the substrate to form a second well region having the first doping type;

forming a floating diffusion region within the second well region; and

forming a gate structure over the substrate between the floating diffusion region and the first photodiode region.

6. The method of claim 1 , further comprising:

forming a dielectric protection layer over the one or more dielectric materials within the trench;

removing the dielectric protection layer from over the first part of the one or more dielectric materials;

selectively etching the one or more dielectric materials not covered by the dielectric protection layer to expose the sidewall and a horizontally extending surface of the substrate; and

forming the doped epitaxial material on the sidewall and the horizontally extending surface of the substrate.

7. The method of claim 6 , further comprising:

forming a gate structure over the substrate; and

forming sidewall spacers along opposing sides of the gate structure, wherein the dielectric protection layer is between the substrate and the sidewall spacers.

8. The method of claim 1 , wherein the doped epitaxial material contacts a sidewall of the one or more dielectric materials.

9. A method of forming an integrated chip, comprising:

etching an upper surface of a substrate to define a trench extending into a well region within the substrate;

forming an isolation structure comprising one or more dielectric materials within the trench;

forming a gate structure over the upper surface of the substrate;

forming a photodiode region within the substrate, wherein the photodiode region is between the gate structure and the trench;

removing the isolation structure from a first part of the trench; and

forming a doped epitaxial material within the first part of the trench, wherein the doped epitaxial material has a greater doping concentration than the well region.

10. The method of claim 9 , wherein the doped epitaxial material continuously extends from within the trench to directly over the upper surface of the substrate.

11. The method of claim 9 ,

wherein removing the isolation structure from the first part of the trench exposes a sidewall of the substrate that is between the isolation structure and the well region; and

wherein the doped epitaxial material is formed on the sidewall of the substrate.

12. The method of claim 9 , wherein the doped epitaxial material extends to a horizontally extending surface of the substrate defining a bottom of the trench.

13. The method of claim 9 , wherein the doped epitaxial material comprises a horizontally extending segment protruding outward from a sidewall of the doped epitaxial material to directly over the photodiode region.

14. The method of claim 9 , wherein the doped epitaxial material within the trench contacts a sidewall of the isolation structure within the trench.

15. The method of claim 9 , wherein the doped epitaxial material extends to a horizontal line disposed along a bottom of the isolation structure, the horizontal line parallel to the upper surface of the substrate.

16. A method of forming an integrated chip, comprising:

etching a substrate to define a trench;

forming an isolation structure within the trench;

forming a gate electrode over an upper surface of the substrate;

forming a photodiode region within the substrate;

forming a dielectric material along sidewalls of the gate electrode, over the upper surface of the substrate, and over the isolation structure;

performing an etching process on the dielectric material and part of the isolation structure according to a masking layer, wherein the etching process exposes surfaces of the substrate; and

forming a doped epitaxial material on the surfaces of the substrate exposed by the etching process.

17. The method of claim 16 , wherein the doped epitaxial material contacts both a sidewall of the isolation structure within the trench and a horizontally extending surface of the substrate defining a bottom of the trench.

18. The method of claim 16 , wherein the doped epitaxial material contacts a top of the photodiode region.

19. The method of claim 16 , wherein the doped epitaxial material has a first doping type and the photodiode region has a second doping type that is different than the first doping type.

20. The method of claim 19 , further comprising:

forming a well region in the substrate, wherein the well region has the first doping type; and

forming the trench within the well region.