IP Library Granted Patent US 10,884,955
Granted Patent B2
US 10,884,955 · App. 16/578,804 · Granted Jan 5, 2021

Stacked and folded above motherboard interposer

Inventors: Morgan Johnson (Portland, OR); Frederick G. Weiss (Newberg, OR)
Assignee: MORGAN/WEISS TECHNOLOGIES INC.
G06F13/16G06F1/32G06F13/4068G11C5/04H01L23/32H01L23/4985H01L23/49838H05K1/0237H05K1/0243H05K1/0296H05K1/111H05K1/115H05K1/147H05K1/181H05K1/189H01L2924/0002H05K1/141H05K7/00H05K2201/095H05K2201/10159H05K2201/10189H05K2201/10378H05K2201/10515H05K2201/10522Y02D10/00Y10T29/4913
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Quick Facts
Patent No.
US 10,884,955
App. No.
16/578,804
Granted
Jan 5, 2021
Kind
B2
Abstract

A computing device has a motherboard circuit substrate having at least a first layer of electrical interconnects, a socket arranged to receive a main processor for the computing device, the socket electrically coupled to at least a portion of the first layer of electrical interconnects, at least two interposer substrates between the main processor and the socket such that the interposer substrate electrically connects to the main processor and the socket, wherein the interposer substrate has a first set of interconnects that electrically connect between the socket and the first layer of electrical interconnects, at least two peripheral circuits on each interposer substrate, the peripheral circuit connected to the main processor through a second set of interconnects on the interposer substrate that connects to the main processor without connecting to the socket or the motherboard circuit substrate, wherein each interposer substrate is folded to allow each peripheral circuit to have an equal path length between the peripheral circuit and the main processor, wherein the at least two interposer substrates are stacked such that the at least two peripheral circuits on each interposer substrate are stacked with the at least two peripheral circuits on another of the at least two interposer substrates.

Claims (9)

1. A computing device, comprising:

a motherboard circuit substrate having at least a first layer of electrical interconnects;

a socket arranged to receive a main processor for the computing device, the socket electrically coupled to at least a portion of the first layer of electrical interconnects;

at least two interposer substrates between the main processor and the socket such that each of the at least two interposer substrates electrically connects to the main processor and the socket, wherein each of the at least two interposer substrates has a first set of interconnects that electrically connect between the socket and the first layer of electrical interconnects; and

at least two peripheral circuits on each of the at least two interposer substrates, the peripheral circuit connected to the main processor through a second set of interconnects on the at least two interposer substrates that electrically connect to the main processor without electrically connecting to the socket or the motherboard circuit substrate, wherein each of the at least two interposer substrates is folded to allow each peripheral circuit to have an equal path length between the peripheral circuit and the main processor, wherein the at least two interposer substrates are stacked such that the at least two peripheral circuits on each interposer substrate are stacked with the at least two peripheral circuits on another of the at least two interposer substrates.

2. The computing device of claim 1 , wherein the at least two peripheral circuits comprise memory modules.

3. The computing device of claim 1 , wherein the at least two interposer substrates comprise three interposer substrates.

4. The computing device of claim 1 , wherein the at least two interposer substrates are stacked such that there is a region of the interposer substrates that are stacked away from the peripheral circuits that are stacked.

5. The computing device of claim 1 , wherein the at least two peripheral circuits on each of the at least two interposer substrates comprises two peripheral circuits on each of the at least two interposer substrates, and each peripheral circuit is stacked on a corresponding one of the at least two interposer substrates.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2021
From: MORGAN/WEISS TECHNOLOGIES, INC.
To: HUAWEI TECHNOLOGIES CO., LTD.
Reel/Frame 055450/0645 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2019
From: JOHNSON, MORGAN; WEISS, FREDERICK G.
To: MORGAN/WEISS TECHNOLOGIES, INC.
Reel/Frame 050459/0679 →
Continuity (7)
Continuation 16288891 · Feb 28, 2019
Continuation 15156211 · May 16, 2016
Continuation 14791302 · Jul 2, 2015
Continuation 13491353 · Jun 7, 2012
Continuation 13163502 · Jun 17, 2011
Provisional Application 61476501 · Apr 18, 2011
Related Publication 20200019519A1 · Jan 16, 2020