Techniques for MRAM MTJ top electrode to metal layer interface including spacer

1. A method for manufacturing a magnetoresistive random-access memory (MRAM) cell, the method including:

forming a spacer layer surrounding at least a magnetic tunnel junction (MTJ) layer and a top electrode of the MRAM cell;

etching the spacer layer to expose a top surface of the top electrode and a top surface of a spacer formed by the spacer layer;

forming an upper etch stop layer directly on the top electrode top surface and the spacer top surface, and wherein the upper etch stop layer has a bottommost edge below an uppermost edge of the top electrode; and

forming an upper metal layer in contact with the top electrode top surface of the MRAM cell;

wherein a width of the upper etch stop layer is greater than a width of a bottom surface of the upper metal layer.

2. A method for manufacturing a magnetoresistive random-access memory (MRAM) cell, the method including:

forming a spacer layer surrounding at least a magnetic tunnel junction (MTJ) layer and a top electrode of the MRAM cell;

etching the spacer layer to expose a top surface of the top electrode and a top surface of a spacer formed by the spacer layer;

forming an upper etch stop layer directly on the top electrode top surface and the spacer top surface; and

forming an upper metal layer in contact with the top electrode top surface of the MRAM cell;

wherein a width of the upper etch stop layer is greater than a width of a bottom surface of the upper metal layer;

wherein the upper etch stop layer overhangs an outer periphery of the spacer top surface, and a portion of the upper etch stop layer that extends beyond the outer periphery of the spacer top surface angles slightly downward.

3. The method of claim 1 wherein the upper etch stop layer comprises silicon nitride (Si 3 N 4 ).

4. The method of claim 1 wherein a width of the spacer top surface combined with a width of the top electrode top surface is greater than approximately 154 nanometers.

5. The method of claim 1 , wherein the spacer layer comprises silicon carbide (SiC).

6. A method for manufacturing a magnetoresistive random-access memory (MRAM) cell, the method including:

forming a spacer layer surrounding at least a magnetic tunnel junction (MTJ) layer and a top electrode of the MRAM cell;

etching the spacer layer to expose a top surface of the top electrode and a top surface of a spacer formed by the spacer layer;

forming an upper etch stop layer over the top electrode top surface and the spacer top surface, wherein a width between bottommost outer edges of the etch stop layer is less than a width between uppermost and outermost edges of the spacer; and

forming a dielectric layer over the spacer top surface and the top electrode top surface;

forming a trench opening and via openings in the dielectric layer, wherein the trench opening exposes the top electrode top surface and a portion of the spacer top surface; and

filling the trench opening and the via openings with a conductive material that directly abuts the top electrode top surface and a portion of the spacer top surface.

7. The method of claim 6 wherein the trench opening exposes less than an entirety of the spacer top surface.

8. The method of claim 1 , further comprising:

prior to forming the spacer layer, forming an etch stop layer disposed over an upper surface of a dielectric layer, wherein the etch stop layer exhibits an opening that leaves at least a portion of an upper surface of an underlying metal line exposed;

forming a bottom electrode layer over the etch stop layer, the bottom electrode layer extends downward through the opening to physically and electrically connect to the underlying metal line; and

forming the magnetic tunnel junction (MTJ) layer over the bottom electrode layer.

9. The method of claim 1 , wherein the upper metal layer directly contacts the top electrode top surface.

10. The method of claim 2 , further comprising:

prior to forming the spacer layer, forming an etch stop layer disposed over an upper surface of a dielectric layer, wherein the etch stop layer exhibits an opening that leaves at least a portion of an upper surface of an underlying metal line exposed;

forming a bottom electrode layer over the etch stop layer, the bottom electrode layer extends downward through the opening to physically and electrically connect to the underlying metal line; and

forming the magnetic tunnel junction (MTJ) layer over the bottom electrode layer.

11. The method of claim 2 wherein the upper etch stop layer comprises silicon nitride (Si 3 N 4 ).

12. The method of claim 2 wherein a width of the spacer top surface combined with a width of the top electrode top surface is greater than approximately 154 nanometers.

13. The method of claim 2 , wherein the spacer layer comprises silicon carbide (SiC).

14. The method of claim 2 , wherein a width of the upper etch stop layer is greater than a width of a bottom surface of the upper metal layer.

15. The method of claim 6 , further comprising:

prior to forming the spacer layer, forming an etch stop layer disposed over an upper surface of a dielectric layer, wherein the etch stop layer exhibits an opening that leaves at least a portion of an upper surface of an underlying metal line exposed;

forming a bottom electrode layer over the etch stop layer, the bottom electrode layer extends downward through the opening to physically and electrically connect to the underlying metal line; and

forming the magnetic tunnel junction (MTJ) layer over the bottom electrode layer.

16. The method of claim 6 wherein the upper etch stop layer comprises silicon nitride (Si 3 N 4 ).

17. The method of claim 6 wherein a width of the spacer top surface combined with a width of the top electrode top surface is greater than approximately 154 nanometers.

18. The method of claim 6 , wherein a width of the upper etch stop layer is greater than a width of a bottom surface of the conductive material.

19. The method of claim 6 , wherein the spacer layer comprises silicon carbide (SiC).

20. The method of claim 1 , wherein the width between bottommost outer edges of the etch stop layer is less than the width between uppermost and outermost edges of the spacer.