IP Library › Granted Patent US 11,063,050
Granted Patent B2
US 11,063,050 · App. 16/582,289 · Granted Jul 13, 2021

Semiconductor device with air gaps and method for fabricating the same

Inventor: Chun-Cheng Liao (New Taipei, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H01L27/10855H01L21/7682H01L21/7687H01L27/10814H01L27/10823H01L27/10876
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Quick Facts
Patent No.
US 11,063,050
App. No.
16/582,289
Granted
Jul 13, 2021
Kind
B2
Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a plurality of plugs positioned above the substrate, a plurality of air gaps positioned adjacent to the plurality of plugs, and a plurality of capacitor structures positioned above the substrate.

Claims (28)

1. A semiconductor device, comprising:

a substrate;

a plurality of plugs positioned above the substrate;

a plurality of air gaps positioned adjacent to the plurality of plugs;

a plurality of capacitor structures positioned above the substrate; and

comprising a plurality of holding structures positioned adjacent to the plurality of plugs;

wherein the plurality of air gaps are positioned above the plurality of holding structures.

2. The semiconductor device of claim 1 , wherein the plurality of holding structures comprise a plurality of top holding structures positioned below the plurality of air gaps, a plurality of middle holding structures positioned below the plurality of top holding structures, and a plurality of bottom holding structures positioned below the plurality of middle holding structures.

3. The semiconductor device of claim 2 , further comprising a plurality of word lines, wherein the plurality of word lines extend along a first direction.

4. The semiconductor device of claim 3 , wherein adjacent pairs of the plurality of middle holding structures are joined to each other along the first direction.

5. The semiconductor device of claim 4 , further comprising a plurality of spacers positioned between the plurality of air gaps and the plurality of plugs.

6. The semiconductor device of claim 5 , wherein the plurality of word lines comprise a plurality of word line insulating layers inwardly positioned in the substrate, a plurality of word line electrodes positioned on the plurality of word line insulating layers, and a plurality of word line capping layers positioned on the plurality of word line electrodes.

7. The semiconductor device of claim 5 , further comprising a plurality of bit lines positioned above the substrate and extending along a second direction, wherein the second direction is perpendicular to the first direction.

8. The semiconductor device of claim 7 , wherein the plurality of bit lines are formed as undulating strips.

9. The semiconductor device of claim 7 , further comprising a plurality of bit line contacts positioned below the plurality of bit lines.

10. The semiconductor device of claim 5 , wherein the plurality of capacitor structures comprise a plurality of capacitor bottom electrodes inwardly positioned above the plurality of plugs, a capacitor insulating layer positioned on the plurality of capacitor bottom electrodes, and a capacitor top electrode positioned on the capacitor insulating layer.

11. A method for fabricating a semiconductor device, comprising:

providing a substrate;

forming a plurality of plugs positioned above the substrate;

forming a plurality of air gaps positioned adjacent to the plurality of plugs;

forming a plurality of capacitor structures positioned above the substrate; and

forming a plurality of holding structures positioned adjacent to the plurality of plugs;

wherein the plurality of air gaps are positioned above the plurality of holding structures.

12. The method for fabricating the semiconductor device of claim 11 , wherein the plurality of holding structures comprise a plurality of top holding structures positioned below the plurality of air gaps, a plurality of middle holding structures positioned below the plurality of top holding structures, and a plurality of bottom holding structures positioned below the plurality of middle holding structures.

13. The method for fabricating the semiconductor device of claim 12 , further comprising forming a plurality of word lines positioned above the substrate, wherein the plurality of word lines extend along a first direction.

14. The method for fabricating the semiconductor device of claim 13 , wherein adjacent pairs of the plurality of middle holding structures are joined to each other along the first direction.

15. The method for fabricating the semiconductor device of claim 14 , further comprising a plurality of spacers positioned between the plurality of air gaps and the plurality of plugs.

16. The method for fabricating the semiconductor device of claim 15 , wherein the plurality of word lines comprise a plurality of word line insulating layers inwardly positioned in the substrate, a plurality of word line electrodes positioned on the plurality of word line insulating layers, and a plurality of word line capping layers positioned on the plurality of word line electrodes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 2, 2019
From: LIAO, CHUN-CHENG
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 050604/0619 →
Continuity (1)
Related Publication 20210091087A1 · Mar 25, 2021
Cited By (1)
US 12,660,159