IP Library › Granted Patent US 10,840,196

Granted Patent B1

US 10,840,196 · App. 16/582,816 · Granted Nov 17, 2020

Trace modulations in connectors for integrated-circuit packages

Inventors: Cemil Geyik (Chandler, AZ); Zhiguo Qian (Chandler, AZ)

Assignee: Intel Corporation

H01L23/64 H01L23/49838 H05K1/0218 H05K1/0242 H05K1/111 H05K2201/09227 H05K2201/09372

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Quick Facts

Patent No.: US 10,840,196
App. No.: 16/582,816
Granted: Nov 17, 2020
Kind: B1

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

Disclosed embodiments include a signal trace in an integrated-circuit device package substrate. Portions of the signal traces, suspend a landing pad in a recess, and a portion of the suspended signal trace is form-factor modulated that is different in cross-section area than other portions of the suspended signal trace.

Claims (47)

1. A signal trace in an integrated-circuit package substrate, comprising:

a landing pad extending over a recess of an integrated-circuit package substrate:

a trace first portion on a surface of the integrated-circuit package substrate, wherein the trace first portion has a first cross-sectional form factor,

a trace second portion contacting and continuing from the trace first portion, wherein the trace second portion has a second cross-sectional form factor that is different from the trace first portion first cross-sectional form factor; and

a trace subsequent portion continuing from the trace second portion, wherein the trace subsequent portion has a subsequent cross-sectional form factor that is different from the trace second portion cross-sectional form factor, wherein the trace subsequent portion is closest to the landing pad compared to the trace first and trace second portions, and wherein the trace subsequent portion, supports the landing pad, wherein the trace second portion cross-sectional form factor has an integral metal-grain structure that transitions from the trace first portion cross-sectional form factor, and wherein the trace second portion cross-sectional form factor has an integral metal-grain structure that transitions from the trace second portion cross-sectional form factor to the trace subsequent portion cross-sectional form factor.

2. The signal trace in the integrated-circuit package substrate of claim 1 ,

wherein the recess is filled with non-electrically conductive dielectric material.

3. The signal trace in the integrated-circuit package substrate of claim 1 , further including:

a post portion continuing and contacting the trace subsequent portion, wherein the post portion contacts the landing pad.

4. The signal trace in the integrated-circuit package substrate of claim 1 , wherein the trace second portion cross-sectional form factor has the same Z-height of the trace first portion cross-sectional form factor, and wherein the trace second portion cross-sectional form factor is modulated to have a wider X-Y width than the trace first portion.

5. The signal trace in the integrated-circuit package substrate of claim 1 , wherein the trace second portion cross-sectional form factor, begins at a circumference boundary of the recess.

6. The signal trace in the integrated-circuit package substrate of claim 1 , wherein the trace second portion cross-sectional form factor, begins at a circumference boundary of the recess, and wherein the trace subsequent portion begins even with a perimeter boundary of the landing pad.

7. The signal trace in the integrated-circuit package substrate of claim 1 , wherein the trace second portion cross-sectional form factor, begins at a circumference boundary of the recess, wherein the trace subsequent portion begins even with a perimeter boundary of the landing pad.

8. The signal trace in the integrated-circuit package substrate of claim 1 , wherein the trace second portion cross-sectional form factor, begins at a circumference boundary of the recess, wherein the trace subsequent portion begins even with a perimeter boundary of the landing pad, and wherein the trace first portion cross-section form factor and the trace subsequent portion cross-section form factor are the same.

9. The signal trace in the integrated-circuit package substrate of claim 1 , wherein the trace second portion cross-sectional form factor has an integral metal-grain structure that transitions from the trace first portion cross-sectional form factor.

10. A signal trace in an integrated-circuit package substrate, comprising:

a landing pad extending over a recess of an integrated-circuit package substrate:

a trace first portion on a surface of the integrated-circuit package substrate, wherein the trace first portion has a first cross-sectional form factor,

ground-stitching structures that at least partially surround the recess, wherein the ground-stitching structures contact at least one common (Vss) source structure in the integrated-circuit package substrate.

11. A signal trace in an integrated-circuit package substrate, comprising:

a landing pad extending over a recess of an integrated-circuit package substrate:

a trace first portion on a surface of the integrated-circuit package substrate, wherein the trace first portion has a first cross-sectional form factor,

a trace subsequent portion continuing from the trace second portion, wherein the trace subsequent portion has a subsequent cross-sectional form factor that is different from the trace second portion cross-sectional form factor, wherein the trace subsequent portion is closest to the landing pad compared to the trace first and trace second portions, and wherein the trace subsequent portion, supports the landing pad, wherein the recess is a first recess with a first characteristic dimension and first characteristic form factor, further including a subsequent recess within the first recess, wherein the subsequent recess is at least partially overshadowed by the landing pad.

12. A signal trace in an integrated-circuit package substrate, comprising:

a landing pad extending over a recess of an integrated-circuit package substrate:

a trace first portion on a surface of the integrated-circuit package substrate, wherein the trace first portion has a first cross-sectional form factor,

a trace subsequent portion continuing from the trace second portion, wherein the trace subsequent portion has a subsequent cross-sectional form factor that is different from the trace second portion cross-sectional form factor, wherein the trace subsequent portion is closest to the landing pad compared to the trace first and trace second portions, and wherein the trace subsequent portion, supports the landing pad, wherein the recess is a first recess with a first characteristic dimension and first characteristic form factor, further including a subsequent recess within the first recess, wherein the subsequent recess is at least partially overshadowed by the landing pad, wherein the landing pad has a characteristic diameter, and wherein the subsequent recess has a characteristic diameter that is less than or equal to the landing-pad characteristic diameter.

13. An integrated-circuit package substrate, comprising:

a signal trace in an integrated-circuit package substrate:

a landing pad extending over a recess of the integrated-circuit package substrate, wherein the signal trace includes:

a trace first portion on a surface of the integrated-circuit package substrate, wherein the trace first portion has a first cross-sectional form factor;

a trace second portion contacting and continuing from the trace first portion, wherein the trace second portion has a second cross-sectional form factor that is modulated and different from the trace first portion first cross-sectional form factor, wherein the trace second portion cross-sectional form factor has the same Z-height of the trace first portion cross-sectional form factor, and wherein the trace second portion cross-sectional form factor is modulated to have a wider X-Y width than the trace first portion;

14. The integrated-circuit package substrate of claim 13 , further including an integrated-circuit die coupled to the landing pad.

15. An integrated-circuit package substrate, comprising:

a signal trace in an integrated-circuit package substrate:

a landing pad extending over a recess of the integrated-circuit package substrate, wherein the signal trace includes:

a trace first portion on a surface of the integrated-circuit package substrate, wherein the trace first portion has a first cross-sectional form factor,

a post portion continuing and contacting the trace subsequent portion, wherein the post portion contacts the landing pad, wherein the recess is a first recess with a first characteristic dimension and first characteristic form factor, further including a subsequent recess within the first recess, wherein the subsequent recess is at least partially overshadowed by the landing pad, wherein the landing pad has a characteristic diameter, and wherein the subsequent recess has a characteristic diameter that is less than or equal to the landing-pad characteristic diameter.

16. The integrated-circuit package substrate of claim 15 , wherein the subsequent recess is filled with non-electrically conductive dielectric material.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2019

From: GEYIK, CEMIL; QIAN, ZHIGUO

To: INTEL CORPORATION

Reel/Frame 050669/0267 →

Cited By (1)

US 12,396,096