Time slotted bus system for multiple coupled digital phase-locked loops

1. An apparatus comprising:

a plurality of digital phase-locked loop circuits; and

a time slotted bus coupling the plurality of digital phase-locked loop circuits, wherein (i) said digital phase-locked loop circuits are configured to exchange parameters between two or more of said plurality of digital phase-locked loop circuits using one or more respective time slots of a plurality of time slots of said time slotted bus, and (ii) at least two of said digital phase-locked loop circuits are configured to transmit parameter data to said time slotted bus during said one or more respective time slots of said plurality of time slots of said time slotted bus.

2. The apparatus according to claim 1 , wherein each of said digital phase-locked loop circuits is configured to fetch data from or present data to said time slotted bus during said one or more respective time slots of said plurality of time slots of said time slotted bus.

3. The apparatus according to claim 1 , wherein said time slotted bus comprises a first bus communicating parameter data and a second bus configured to identify said time slots.

4. The apparatus according to claim 3 , wherein said time slotted bus further comprises an address generator driving said second bus.

5. The apparatus according to claim 4 , wherein said address generator is configured to cycle through a number of addresses corresponding to the time slots associated with said plurality of digital phase-locked loop circuits.

6. The apparatus according to claim 5 , wherein said number of addresses is an integer multiple of the number of said digital phase-locked loop circuits.

7. The apparatus according to claim 1 , wherein each of said digital phase-locked loop circuits comprises:

a set of programmable registers configured to identify one or more time slots associated with each of said digital phase-locked loop circuits; and

a decoder configured to generate one or more control signals based on time slot information received from the time slotted bus and values stored in the set of programmable registers.

8. The apparatus according to claim 1 , wherein each of said digital phase-locked loop circuits comprises:

a set of programmable registers configured to identify one or more time slots at which the digital phase-locked loop circuits fetch data from the time slotted bus; and

an accumulator configured to accumulate data fetched from time slotted bus during the time slots indicated by values stored in the set of programmable registers.

9. The apparatus according to claim 1 , wherein said parameters comprise one or more of an unfiltered offset value or a filtered offset value.

10. The apparatus according to claim 1 , wherein:

one or more of said plurality of digital phase-locked loop circuits are configured as sourcing digital phase-locked loop circuits; and

at least one other of said plurality of digital phase-locked loops is configured as a receiving digital phase-locked loop circuit.

11. A method of coupling a plurality of digital phase-locked loop circuits comprising:

broadcasting addresses corresponding to predefined time slots of a time slotted bus connecting said plurality of digital phase-locked loop circuits; and

exchanging parameters between two or more of said plurality of digital phase-locked loop circuits using one or more of said predefined time slots of said time slotted bus associated with said two or more of said plurality of digital phase-locked loop circuits.

12. The method according to claim 11 , wherein said parameters comprise one or more of an unfiltered offset value or a filtered offset value.

13. The method according to claim 11 , wherein:

one or more of said plurality of digital phase-locked loop circuits are configured as sourcing digital phase-locked loop circuits; and

at least one other of said plurality of digital phase-locked loop circuits is configured as a receiving digital phase-locked loop circuit.

14. The method according to claim 11 , wherein said plurality of digital phase-locked loop circuits are configured to synchronize at least one of (i) a plurality of telecommunications networks and (ii) a mobile network base station to a telecommunications network.

15. An apparatus comprising:

a plurality of digital phase-locked loop circuits; and

a time slotted bus coupling the plurality of digital phase-locked loop circuits, wherein said plurality of digital phase-locked loop circuits are configured to exchange parameters between two or more of said plurality of digital phase-locked loops using one or more respective time slots of a plurality of time slots of said time slotted bus, and said time slotted bus comprises a first portion communicating parameter data and a second portion configured to identify said time slots.

16. The apparatus according to claim 15 , wherein said time slotted bus further comprises an address generator configured to identify said time slots.

17. The apparatus according to claim 16 , wherein said address generator is configured to cycle through a number of addresses corresponding to the time slots associated with said plurality of digital phase-locked loop circuits.

18. The apparatus according to claim 17 , wherein said number of addresses is an integer multiple of the number of said digital phase-locked loop circuits.

19. The apparatus according to claim 15 , wherein said parameters comprise one or more of an unfiltered offset value or a filtered offset value.

20. The apparatus according to claim 15 , wherein:

one or more of said plurality of digital phase-locked loop circuits are configured as sourcing digital phase-locked loop circuits; and

at least one other of said plurality of digital phase-locked loop circuits is configured as a receiving digital phase-locked loop circuit.