Semiconductor device and method of fabricating the same

1. A semiconductor device, comprising:

a semiconductor substrate comprising a memory region and a logic region from the memory region;

a memory cell disposed in the memory region;

a first logic transistor disposed in the memory region and disposed adjacent to the memory cell;

a second logic transistor disposed in the logic region,

a patterned conductive layer extending above the semiconductor substrate and across the memory region and the logic region, wherein the patterned conductive layer includes a plurality of conductive portions electrically coupled to the first logic transistor and the second logic transistor respectively;

wherein the second logic transistor generates a memory control signal and transmits the memory control signal to the first logic transistor via the plurality of conductive portions, and the first logic transistor controls operation of the memory cell in response to the memory control signal provided by the second logic transistor.

2. The semiconductor device of claim 1 , wherein the memory control signal includes a command signal.

3. The semiconductor device of claim 1 , wherein the second logic transistor serves as a component of a processing unit defined by a control unit (CU) and an arithmetic logic unit (ALU).

4. The semiconductor device of claim 1 , wherein the memory cell comprises a memory transistor communicating with the second logic transistor via the first logic transistor.

5. The semiconductor device of claim 1 , further comprising a first semiconductor memory including the memory cell and the first logic transistor, and a second semiconductor memory, wherein the first semiconductor memory and the second semiconductor memory are a dynamic random access memory (DRAM), wherein the semiconductor device further comprises a processing unit including the second logic transistor, and a static random-access memory (SRAM),

wherein data latency of the first semiconductor memory is less than or equal to that of the second semiconductor memory, and data latency of the SRAM is less than or equal to that of the first semiconductor memory.

6. The semiconductor device of claim 5 , wherein data density of the first semiconductor memory is less than or equal to that of the second semiconductor memory, and data density of the SRAM is less than or equal to that of the first semiconductor memory.

7. The semiconductor device of claim 1 , wherein the first logic transistor is level with the second logic transistor.

8. The semiconductor device of claim 1 , further comprising:

a dielectric layer disposed on the semiconductor substrate, wherein the memory cell includes a buried gate disposed beneath the dielectric layer, wherein the first logic transistor includes a first logic gate disposed in the dielectric layer, and wherein the second logic transistor includes a second logic gate disposed in the dielectric layer.

9. The semiconductor device of claim 1 , further comprising:

a guard ring disposed on the semiconductor substrate and surrounding the memory cell, the first logic transistor and the second logic transistor.

10. The semiconductor device of claim 1 , wherein the first logic transistor converts the memory control signal into a word line select signal and a bit line select signal, which are transmitted on the patterned conductive layer.

11. The semiconductor device of claim 1 , wherein the first logic transistor and the second logic transistor have the same semiconductor structure profile.

12. The semiconductor device of claim 1 , wherein the first logic transistor and the second logic transistor have the same component.

13. The semiconductor device of claim 1 , wherein the component of the first logic transistor and the component of second logic transistor include the same semiconductor material.