Active bridge chiplet with integrated cache
A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via an active bridge chiplet. The active bridge chiplet is an active silicon die that bridges GPU chiplets and allows partitioning of systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.
1. A system, comprising:
a central processing unit (CPU) communicably coupled to a first graphics processing unit (GPU) chiplet of a GPU chiplet array, wherein the GPU chiplet array includes:
the first GPU chiplet communicably coupled to the CPU via a bus; and
a second GPU chiplet communicably coupled to the first GPU chiplet via an active bridge chiplet, wherein the active bridge chiplet includes a level of cache memory that is shared by the first and second GPU chiplets of the GPU chiplet array, and
wherein the first GPU chiplet is configured to request data, associated with a memory access request, from the active bridge chiplet.
2. The system of claim 1 , wherein the level of cache memory comprises a unified cache memory that is coherent across the first and second GPU chiplets of the GPU chiplet array.
3. The system of claim 1 , wherein the level of cache memory comprises a memory-attached last level of cache positioned between a memory controller of the first GPU chiplet and an off-die memory.
4. The system of claim 1 , wherein the active bridge chiplet communicably couples GPU chiplets in the GPU chiplet array.
5. The system of claim 1 , wherein the first GPU chiplet further includes a scalable data fabric configured to receive the memory access request from the CPU.
6. The system of claim 1 , wherein the active bridge chiplet comprises a memory crossbar for chiplet-to-chiplet communications between GPU chiplets of the GPU chiplet array.
7. The system of claim 1 , further comprising:
a first cache memory hierarchy at the first GPU chiplet, wherein a first level of the first cache memory hierarchy is coherent within the first GPU chiplet; and
a second cache memory hierarchy at the second GPU chiplet, wherein a first level of the second cache memory hierarchy is coherent within the second GPU chiplet.
8. The system of claim 7 , wherein the level of cache memory at the active bridge chiplet comprises a unified cache memory including both a last level of the first cache memory hierarchy and a last level of the second cache memory hierarchy, wherein the unified cache memory is coherent across the first and second GPU chiplets of the GPU chiplet array.
9. A method, comprising:
receiving, at a first GPU chiplet of a GPU chiplet array, a memory access request from a central processing unit (CPU);
determining, at an active bridge chiplet controller of the first GPU chiplet, that data associated with the memory access request is cached at an active bridge chiplet shared by the first GPU chiplet and a second GPU chiplet of the GPU chiplet array;
routing the memory access request to a unified last level cache at the active bridge chiplet; and
returning data associated with the memory access request to the CPU.
10. The method of claim 9 , wherein routing the memory access request further includes a scalable data fabric requesting data associated with the memory access request from the active bridge chiplet.
11. The method of claim 10 , further comprising:
returning data associated with the memory access request to the first GPU chiplet via the scalable data fabric.
12. The method of claim 9 , wherein receiving the memory access request includes a scalable data fabric receiving the memory access request from the CPU.
13. The method of claim 12 , further comprising:
receiving data associated with the memory access request from the active bridge chiplet via the scalable data fabric.
14. The method of claim 9 , further comprising:
caching data at a unified cache memory of the active bridge chiplet, wherein the unified cache memory includes:
a last level of a first cache memory hierarchy at the first GPU chiplet, wherein a first level of the first cache memory hierarchy is coherent within the first GPU chiplet; and
a last level of a second cache memory hierarchy at a second GPU chiplet of the GPU chiplet array, wherein a first level of the second cache memory hierarchy is coherent within the second GPU chiplet.
15. A processor, comprising:
a central processing unit (CPU);
a GPU chiplet array including a first GPU chiplet, the first GPU chiplet including an active bridge chiplet controller;
a unified last level cache; and
wherein the processor is configured to:
receive, at the first GPU chiplet, a memory access request from the CPU;
determine, at the active bridge chiplet controller of the first GPU chiplet, that data associated with the memory access request is cached at an active bridge chiplet shared by the first GPU chiplet and a second GPU chiplet of the GPU chiplet array;
route the memory access request to the unified last level cache at the active bridge chiplet; and
return data associated with the memory access request to the CPU.
16. The processor of claim 15 , wherein the processor is configured to request, via a scalable data fabric, data associated with the memory access request from the active bridge chiplet.
17. The processor of claim 16 , wherein the processor is configured to return data associated with the memory access request to the first GPU chiplet via the scalable data fabric.
18. The processor of claim 15 , wherein the processor is configured to receive, via a scalable data fabric, the memory access request from the CPU.
19. The processor of claim 18 , wherein the first GPU chiplet is configured to receive data associated with the memory access request from the active bridge chiplet via the scalable data fabric.