Gate structure and methods thereof
A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.
1. A device, comprising:
a substrate including a first substrate region and a second substrate region different than the first substrate region, wherein the first substrate region and the second substrate region are both free of any shallow trench isolation feature;
a first transistor disposed within the first substrate region, wherein the first transistor includes a first gate stack having a first height, and wherein the first gate stack includes a first metal gate layer having a first thickness; and
a second transistor disposed within the second substrate region, wherein the second transistor includes a second gate stack having a second height less than the first height, and wherein the second gate stack includes a second metal gate layer having a second thickness substantially equal to the first thickness of the first metal gate layer;
wherein a top surface of the first gate stack is substantially level with a top surface of the second gate stack.
2. The device of claim 1 , wherein the first substrate region includes a trench, wherein the first gate stack includes a gate dielectric, and wherein at least part of the gate dielectric is disposed within the trench.
3. The device of claim 1 , wherein the first transistor includes a high-voltage transistor (HVT), and wherein the second transistor includes a low-voltage transistor (LVT).
4. The device of claim 1 , wherein a ratio of the first thickness of the first metal gate layer to the first height of the first gate stack is in a range of about 50-80%.
5. The device of claim 1 , wherein a ratio of the second thickness of the second metal gate layer to the second height of the second gate stack is greater than about 80%.
6. A semiconductor device, comprising:
a high-voltage transistor (HVT) disposed within a first region of a substrate, wherein the HVT includes a first gate stack having a first height;
a first low-voltage transistor (LVT) within a second region of the substrate, wherein the first LVT includes a second gate stack having a second height less than the first height; and
a second LVT within a third region of the substrate, wherein the second LVT includes a third gate stack having a third height less than the first height;
wherein the first region of the substrate, the second region of the substrate, and the third region of the substrate are each free of any shallow trench isolation feature; and
wherein top surfaces of each of the first gate stack, the second gate stack, and the third gate stack are substantially level with each other.
7. The semiconductor device of claim 6 , wherein the first region of the substrate includes a trench, wherein the first gate stack includes a first gate dielectric, and wherein at least part of the first gate dielectric is disposed within the trench.
8. The semiconductor device of claim 7 , wherein a top surface of the first gate dielectric is level with a top surface of the substrate.
9. The semiconductor device of claim 7 , further including a source region and a drain region formed within the first region and on either side of the trench, wherein the trench has a first depth, and wherein the source region and the drain region extend into the substrate a second depth greater than the first depth.
10. The semiconductor device of claim 7 , wherein the trench has a first width along a plane parallel to a top surface of the substrate, wherein the trench has a second width along a plane parallel to a bottom surface of the trench, and wherein the second width is less than the first width.
11. A semiconductor device, comprising:
a first transistor disposed within a high-voltage region of a substrate, wherein the first transistor includes a first gate stack having a first height, wherein the high-voltage region includes a trench, wherein the first gate stack includes a first gate dielectric portion disposed within the trench, and wherein the first gate stack includes a second gate dielectric portion that extends above the trench;
a second transistor disposed within a low-voltage region of the substrate, wherein the second transistor includes a second gate stack having a second height less than the first height; and
first source and drain regions disposed within the high-voltage region and on either side of the trench, wherein the trench has a first depth, and wherein the first source and drain regions extend into the substrate a second depth greater than the first depth;
wherein the high-voltage region and the low-voltage region are each free of any shallow trench isolation feature; and
wherein a top surface of the first gate stack is substantially level with a top surface of the second gate stack.
12. The semiconductor device of claim 11 , wherein the first gate dielectric portion disposed within the trench includes a silicon oxide layer or a silicon oxynitride layer, and wherein the second gate dielectric portion that extends above the trench includes a high-K dielectric layer.
13. The semiconductor device of claim 12 , wherein a thickness of the silicon oxide layer or the silicon oxynitride layer is substantially equal to the first depth of the trench.
14. The semiconductor device of claim 11 , further comprising second source and drain regions disposed with the low-voltage region and on either side of the second gate stack, wherein the second source and drain regions extend into the substrate a third depth less than both the first depth and the second depth.
15. The semiconductor device of claim 11 , wherein the first transistor includes a high-voltage transistor, and wherein the second transistor includes one of a logic transistor, a static random access memory (SRAM) transistor, and an input/output (I/O) transistor.
16. The semiconductor device of claim 11 , wherein the trench has a first width along a plane parallel to the top surface of the substrate, and wherein the trench has a second width different than the first width along a plane parallel to a bottom surface of the trench.
17. The semiconductor device of claim 16 , wherein the second width is less than the first width.
18. The semiconductor device of claim 11 , wherein the first gate stack includes a first metal gate layer having a first thickness, and wherein the second gate stack includes a second metal gate layer having a second thickness substantially equal to the first thickness of the first metal gate layer.
19. The device of claim 3 , wherein the LVT includes one of a logic transistor, a static random access memory (SRAM) transistor, and an input/output (I/O) transistor.
20. The semiconductor device of claim 6 , wherein the first LVT has a first gate dielectric having a first thickness, and wherein the second LVT has a second gate dielectric having a second thickness different than the first thickness.