Static random access memory with write assist adjustment
View Patent ↗The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a boost circuit configured to output a first negative voltage at a first output terminal, and an adjustment circuit configured to couple the first negative voltage to a second negative voltage higher than the first negative voltage. The adjustment circuit can include a transistor, and a second output terminal electrically connected to the first output terminal. The transistor can include a first source/drain terminal, a second source/drain terminal, and a gate terminal. The first source/drain terminal can be electrically coupled to the second output terminal. The second source/drain terminal can be electrically connected to a voltage source. The gate terminal can be electrically connected to a ground voltage supply.
1. A write assist circuit, comprising:
a boost circuit configured to output a first negative voltage at a first output terminal; and
an adjustment circuit configured to increase the first negative voltage to a second negative voltage, higher than the first negative voltage, at the first output terminal, wherein the adjustment circuit comprises:
a transistor comprising a first source/drain terminal, a second source/drain terminal, and a gate terminal; and
a second output terminal electrically connected to the first output terminal, wherein:
the first source/drain terminal is electrically coupled to the second output terminal;
the second source/drain terminal is electrically connected to a voltage source; and
the gate terminal is electrically connected to a ground voltage supply source.
2. The write assist circuit of claim 1 , wherein the second source/drain terminal is electrically connected to the ground voltage source.
3. The write assist circuit of claim 1 , wherein the voltage source is configured to provide a positive voltage.
4. The write assist circuit of claim 1 , wherein the second output terminal is electrically shorted to the first output terminal via a wire.
5. The write assist circuit of claim 1 , wherein the adjustment circuit further comprises a plurality of transistors, wherein gate terminals of the plurality transistors are electrically connected to the ground voltage source, and source/drain terminals of the plurality transistors are electrically connected to the second output terminal.
6. The write assist circuit of claim 1 , wherein the adjustment circuit further comprises a multiplexer, wherein an input terminal of the multiplexer is electrically connected to the first source/drain terminal, and an output terminal of the multiplexer is electrically connected to the second output terminal.
7. The write assist circuit of claim 1 , wherein the ground voltage source is configured to provide a fixed logic low level.
8. A memory device, comprising:
an array of memory cells;
a write driver circuit configured to provide a reference voltage; and
a write assist circuit configured to couple the reference voltage from the write driver circuit to a first negative voltage, wherein the write assist circuit comprises:
a boost circuit configured to provide a second negative voltage lower than the first negative voltage; and
an adjustment circuit configured to increase the second negative voltage to the first negative voltage, wherein:
the adjustment circuit comprises a transistor with a gate terminal, a first source/drain terminal, and a second source/drain terminal;
the gate terminal is electrically connected to a first voltage source;
the first source/drain terminal is electrically connected to a second voltage source; and
the second source/drain terminal is electrically connected to the boost circuit and couples the second negative voltage to the first negative voltage.
9. The memory device of claim 8 , wherein each memory cell in the array of memory cells comprises a pass gate transistor, wherein a threshold voltage of the pass gate transistor is substantially equal to a threshold voltage of the transistor.
10. The memory device of claim 8 , wherein the first voltage source is ground.
11. The memory device of claim 8 , wherein the second voltage source is configured to output a fixed logic high level.
12. The memory device of claim 8 , wherein the adjustment circuit further comprises a multiplexer configured to electrically couple the second source/drain terminal to the boost circuit.
13. The memory device of claim 8 , wherein:
the write driver circuit is configured to output the reference voltage at a bitline of the array of memory cells;
the boost circuit is configured to couple the reference voltage to the second negative voltage at the bitline; and
the adjustment circuit is configured to increase the second negative voltage the first negative voltage at the bitline.
14. The memory device of claim 8 , wherein the adjustment circuit further comprises an other transistor, wherein:
the other transistor comprises an other gate terminal, an other first source/drain terminal, and an other second source/drain terminal;
the other gate terminal is electrically connected to the first voltage source;
the other first source/drain terminal is electrically connected to the second voltage source; and
the other second source/drain terminal is electrically shorted to the second source/drain terminal of the transistor.
15. The memory device of claim 8 , wherein the adjustment circuit further comprises an other transistor, wherein:
the other transistor comprises an other gate terminal, an other first source/drain terminal, and an other second source/drain terminal;
the other gate terminal is electrically connected to the first voltage source;
the other first source/drain terminal is electrically connected to the second voltage source; and
the other second source/drain terminal is electrically connected to the boost circuit.
16. The memory device of claim 15 , wherein the adjustment circuit further comprises a multiplexer electrically connected to the second source/drain terminal of the transistor and to the other second source/drain terminal of the other transistor.
17. A method for a memory write operation, comprising:
receiving memory address information associated with the memory write operation for one or more memory cells;
providing a reference voltage to one or more bitlines coupled to the one or more memory cells;
coupling, with a boost circuit, the reference voltage to a first negative voltage at the one or more bitlines; and
increasing, with one or more pull-up transistors, the first negative voltage to a second negative voltage higher than the first negative voltage, at the one or more bitlines based on the memory address information.
18. The method of claim 17 , wherein the providing the reference voltage comprises initializing, with a pull-down transistor, the reference voltage to a ground level prior to coupling the reference voltage to the first and increasing the first negative voltage to the second negative voltages.
19. The method of claim 17 , wherein the increasing the first negative voltage to the second negative voltage comprises biasing, via a voltage source configured to output a static logic low level, a gate terminal of each of the one or more pull-up transistors to the static logic low level.
20. The method of claim 17 , wherein the increasing the first negative voltage to the second negative voltage comprises:
biasing a source terminal of each of the one or more pull-up transistors; and
coupling, with a multiplexer, a drain terminal of each of the one or more pull-up transistors to the one or more bitlines with the second negative voltage.