IP Library Granted Patent US 10,607,897
Granted Patent B2
US 10,607,897 · App. 16/589,032 · Granted Mar 31, 2020

Semiconductor device and method for fabricating the same

Inventors: Fu-Jung Chuang (Kaohsiung, TW); Ching-Ling Lin (Kaohsiung, TW); Po-Jen Chuang (Kaohsiung, TW); Yu-Ren Wang (Tainan, TW); Wen-An Liang (Tainan, TW); Chia-Ming Kuo (Kaohsiung, TW); Guan-Wei Huang (Tainan, TW); Yuan-Yu Chung (Tainan, TW); I-Ming Tseng (Kaohsiung, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L21/823878H01L21/76224H01L21/823821H01L27/0924
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Quick Facts
Patent No.
US 10,607,897
App. No.
16/589,032
Granted
Mar 31, 2020
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.

Claims (22)

1. A method for fabricating semiconductor device, comprising:

providing a substrate having a first region and a second region;

forming a first fin-shaped structure on the first region;

removing part of the first fin-shaped structure to form a first trench;

forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and

planarizing the dielectric layer to form a first single diffusion break (SDB) structure.

2. The method of claim 1 , further comprising:

forming the first fin-shaped structure on the first region and a second fin-shaped structure on the second region;

removing part of the first fin-shaped structure and part of the second fin-shaped structure to form the first trench and a second trench;

forming the dielectric layer in the first trench and the second trench; and

planarizing the dielectric layer to form the first SDB structure and a second SDB structure.

3. The method of claim 2 , further comprising forming a liner in the first trench and the second trench before forming the dielectric layer.

4. The method of claim 3 , wherein the liner and the dielectric layer comprise different materials.

5. The method of claim 3 , wherein the liner comprises silicon oxide.

6. The method of claim 2 , further comprising:

forming a first gate structure on the first SDB structure and the first fin-shaped structure and a second gate structure on the second SDB structure and the second fin-shaped structure;

forming a first source/drain region adjacent to the first gate structure and a second source/drain region adjacent to the second gate structure; and

performing a replacement metal gate (RMG) process to transform the first gate structure and the second gate structure into a first metal gate and a second metal gate.

7. The method of claim 2 , wherein each of the first fin-shaped structure and the second fin-shaped structure is disposed extending along a first direction and the first SDB structure and the second SDB structure are disposed extending along a second direction.

8. The method of claim 7 , wherein the first direction is orthogonal to the second direction.

9. The method of claim 1 , wherein a concentration proportion of oxygen in SiOCN is between 30% to 60%.

10. The method of claim 1 , wherein a stress of the first SDB structure is between 100 MPa to −500 MPa.

Priority Claims (1)
TW 107120159 A · Jun 12, 2018 · national
Continuity (2)
Division 16030871 · Jul 10, 2018
Related Publication 20200035568A1 · Jan 30, 2020