Vertical structure for semiconductor device
The present disclosure describes a method to form a fin field effect transistor (finFET) and a nano-sheet transistor on a substrate. The method can include forming first and second vertical structures over a substrate, where each of the first and the second vertical structures can include a buffer region and a first channel layer formed over the buffer region. The method can further include disposing a masking layer over the first channel layer of the first and second vertical structures, removing a portion of the first vertical structure to form a first recess, forming a second channel layer in the first recess, forming a second recess in the second channel layer, and disposing an insulating layer in the second recess.
1. A method, comprising:
forming first and second vertical structures over a substrate, wherein each of the first and the second vertical structures comprises a buffer region and a first channel layer formed over the buffer region;
removing a portion of the first vertical structure to form a first recess;
forming a second channel layer in the first recess;
forming a second recess in the second channel layer; and
disposing an insulating layer in the second recess.
2. The method of claim 1 , wherein the removing the portion of the first vertical structure comprises:
forming a masking layer over the first channel layer of the first and second vertical structures;
removing the masking layer of the first vertical structure to expose the first channel layer of the first vertical structure; and
etching the first channel layer of the first vertical structure.
3. The method of claim 1 , wherein the forming the second channel layer over the first recess comprises epitaxially growing a semiconductor layer in the first recess.
4. The method of claim 1 , wherein the forming the second channel layer in the first recess comprises capping the first channel of the second vertical structure with a masking layer.
5. The method of claim 1 , wherein the forming the second recess in the second channel layer comprises:
forming a hard mask layer over edge portions of the second channel layer while exposing a central portion of the second channel layer; and
etching the central portion of the second channel layer defined by a masking layer.
6. The method of claim 5 , wherein the forming the second recess in the second channel layer further comprises capping the first channel of the second vertical structure with the masking layer during the etching of the central portion of the second channel layer.
7. The method of claim 1 , wherein the disposing the insulating layer comprises:
depositing a dielectric material in the second recess to cover a bottom and side surfaces of the second recess; and
etching a portion of the deposited dielectric material to expose a portion of the side surfaces of the second recess.
8. The method of claim 1 , wherein the forming the first and the second vertical structures comprises:
epitaxially growing a multilayer nano-sheet stack with alternating first and second nano-sheet layers over the substrate;
forming a masking layer over the multilayer nano-sheet stack;
removing portions of the multilayer nano-sheet stack using the masking layer to form a plurality of trenches; and
filling the plurality of trenches with an insulating material.
9. A method, comprising:
forming first and second nano-sheet stacks, wherein each of the first and second nano-sheet stacks comprises a vertical structure having alternating first and second nano-sheet layers;
replacing the first nano-sheet stack with a channel layer;
forming a recess in the channel layer; and
removing each of the second nano-sheet layers from a portion of the second nano-sheet stack to expose a top surface or a bottom surface of each of the first nano-sheet layers in the portion of the second nano-sheet stack.
10. The method of claim 9 , wherein the replacing the first nano-sheet stack with the channel layer comprises:
removing a portion of the first nano-sheet stack to form an other recess; and
epitaxially growing a single semiconductor layer in the other recess.
11. The method of claim 9 , wherein the forming the recess in the channel layer comprises:
forming a masking layer over a portion of the channel layer; and
etching the channel layer using the masking layer.
12. The method of claim 9 , further comprising depositing a dielectric layer in the recess.
13. The method of claim 9 , further comprising:
forming a first metal gate structure surrounding each of the first nano-sheet layers in the portion of the second nano-sheet stack; and
forming a second metal gate structure over an other top surface and side surfaces of the recessed channel layer, wherein a bottom of the recessed channel layer is in contact with the substrate.
14. The method of claim 9 , further comprising forming a first polysilicon structure over the portion of the second nano-sheet stack and a second polysilicon structure over the recessed channel layer, wherein a length of the second polysilicon structure is longer than an other length of the first polysilicon structure.
15. A method, comprising:
forming a nano-sheet stack over a substrate;
etching a first portion of the nano-sheet stack to form first and second vertical structures, wherein each of the first and second vertical structures comprises a second portion of the nano-sheet stack;
removing the second portion of the nano-sheet stack of the first vertical structure with the second vertical structure being capped with a hard mask stack; and
forming a channel layer by selectively growing an epitaxial layer at the removed second portion of the nano-sheet stack of the first vertical structure with the second portion of the nano-sheet stack of the second vertical structure being capped with the hard mask stack.
16. The method of claim 15 , wherein etching the first portion of the nano-sheet stack comprises forming first and second buffer regions under the second portion of the nano-sheet stack of the first and second vertical structures, respectively, and wherein removing the second portion of the nano-sheet stack of the first vertical structure comprises exposing a first top surface of the first buffer region with a second top surface of the second buffer region being capped by the hard mask stack.
17. The method of claim 15 , wherein forming the nano-sheet stack comprises epitaxially growing alternating silicon and silicon germanium layers, and wherein forming the channel layer comprises epitaxially growing another silicon layer substantially coplanar with the alternating silicon and silicon germanium layers.
18. The method of claim 15 , further comprising forming a recess structure in the channel layer with the second vertical structure being capped with the hard mask stack.
19. The method of claim 15 , further comprising forming first and second gate structures over the channel layer and over the second vertical structure, respectively, wherein a gate length of the second gate structure is less than an other gate length of the first gate structure.
20. The method of claim 15 , wherein the channel layer is doped using an ion implantation process.