Stack semiconductor packages having wire-bonding connection structure

1. A semiconductor package comprising:

a package substrate having a hole pattern including a first through hole extending in a first direction and a second through hole extending in a second direction substantially perpendicular to the first direction;

at least one first semiconductor chip disposed on a surface of the package substrate to overlap with the first through hole;

at least one second semiconductor chip disposed on the surface of the package substrate to overlap with the second through hole;

first bonding wires passing through the first through hole to electrically connect the at least one first semiconductor chip to the package substrate; and

second bonding wires passing through the second through hole to electrically connect the at least one second semiconductor chip to the package substrate,

wherein the at least one second semiconductor chip is stacked on the at least one first semiconductor chip on the surface of the package substrate,

wherein the hole pattern has a cross shape provided by the first and second through holes intersecting each other.

2. The semiconductor package of claim 1 , further comprising:

first chip pads disposed on the at least one first semiconductor chip to overlap with the first through hole; and

second chip pads disposed on the at least one second semiconductor chip to overlap with the second through hole,

wherein the first bonding wires are bonded to the first chip pads, and

wherein the second bonding wires are bonded to the second chip pads.

3. The semiconductor package of claim 2 ,

wherein the first chip pads are disposed on a central region of the first semiconductor chip; and

wherein the second chip pads are disposed on a central region of the second semiconductor chip.

4. The semiconductor package of claim 1 ,

wherein the at least one first semiconductor chip is disposed on the package substrate; and

wherein the at least one second semiconductor chip is disposed on the at least one first semiconductor chip.

5. The semiconductor package of claim 1 ,

wherein the at least one first semiconductor chip includes two first semiconductor chips disposed on a surface of the package substrate to be substantially parallel with each other; and

wherein the at least one second semiconductor chip includes two second semiconductor chips disposed on the two first semiconductor chips to be parallel with each other.

6. The semiconductor package of claim 5 ,

wherein the two first semiconductor chips are disposed to intersect the two second semiconductor chips at substantially a right angle; and

wherein the two first semiconductor chips overlap with the two second semiconductor chips at four overlapping regions on a surface of the package substrate.

7. The semiconductor package of claim 1 , wherein the at least one first semiconductor chip and the least one second semiconductor chip have the same size.

8. The semiconductor package of claim 1 ,

wherein the at least one first semiconductor chip includes two first semiconductor chips disposed on a surface of the package substrate to be parallel with each other;

wherein the at least one second semiconductor chip includes a single second semiconductor chip disposed on the two first semiconductor chips; and

wherein the single second semiconductor chip is disposed to overlap with the second through hole exposed between the two first semiconductor chips.

9. The semiconductor package of claim 1 , wherein the package substrate includes:

first chip connection pads to which the first bonding wires are bonded; and

second chip connection pads to which the second bonding wires are bonded.

10. The semiconductor package of claim 9 ,

wherein the package substrate further includes outer connection pads that are disposed on a surface of the package substrate and electrically connected to the first and second chip connection pads; and

wherein the outer connection pads and the first and second chip connection pads are disposed on a same surface.

11. A semiconductor package comprising:

a package substrate configured to have a hole pattern including a first through hole and a second through hole intersecting each other and configured to have first to fourth substrate regions defined by the hole pattern;

two first semiconductor chips disposed on a first surface of the package substrate to cross over the first through hole, wherein one of the two first semiconductor chips overlaps the first and second substrate regions and the other of the two first semiconductor chips overlaps the third and fourth substrate regions;

two second semiconductor chips disposed on the two semiconductor chips to cross over the second through hole, wherein one of the two second semiconductor chips overlaps the first and third substrate regions and the other of the two second semiconductor chips overlaps the second and fourth substrate regions;

first bonding wires passing through the first through hole to electrically connect the two first semiconductor chips to the package substrate; and

second bonding wires passing through the second through hole to electrically connect the two second semiconductor chips to the package substrate.

12. The semiconductor package of claim 11 ,

wherein the first through hole extends in a first direction; and

wherein the second through hole extends in a second direction substantially perpendicular to the first direction.

13. The semiconductor package of claim 11 , further comprising:

first chip pads disposed on the two first semiconductor chips to overlap with the first through hole; and

second chip pads disposed on the two second semiconductor chips to overlap with the second through hole,

wherein the first bonding wires are bonded to the first chip pads, and

wherein the second bonding wires are bonded to the second chip pads.

14. The semiconductor package of claim 11 ,

wherein the package substrate further includes first and second chip connection pads disposed on a second surface of the package substrate opposite to the first and second semiconductor chips; and

wherein the first and second bonding wires are bonded to the first and second chip connection pads.

15. The semiconductor package of claim 14 , wherein the package substrate further includes:

outer connection pads disposed on the second surface of the package substrate; and

outer connection members attached to the outer connection pads,

wherein the outer connection pads are electrically connected to the first and second chip connection pads.

16. The semiconductor package of claim 15 , wherein the outer connection pads are disposed on the first to fourth substrate regions.