Semiconductor memory having both volatile and non-volatile functionality and method of operating
Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.
1. A semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of at least one row and a plurality of columns or at least one column and a plurality of rows, wherein each of said semiconductor memory cells comprises:
a fin structure extending from a substrate, said fin structure comprising a floating body region configured to be charged to a level indicative of a state of the memory cell to store the state as volatile memory; and
a floating gate or trapping layer insulated from said floating body region and being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory;
wherein charge flow into said floating body region upon restoration of power to said memory cell is non-algorithmically determined by said charge stored in said floating gate or trapping layer; and
wherein said charge flow into said floating body region upon restoration of power to said memory cell occurs to at least two of said memory cells.
2. The semiconductor memory array of claim 1 , further comprising first and second regions in electrical contact with said floating body region, wherein both of said first and second regions have a conductivity type different from a conductivity type of said floating body region.
3. The semiconductor memory array of claim 1 , further comprising an isolation layer that isolates said floating body region from said substrate.
4. The semiconductor memory array of claim 3 , wherein said isolation layer comprises a buried oxide insulating layer.
5. The semiconductor memory array of claim 3 , wherein said isolation layer comprises a buried layer having a conductivity type different from a conductivity type of said floating body region.
6. The semiconductor memory array of claim 1 , wherein said floating gate or trapping layer is insulated from said floating body region by an insulating layer.
7. The semiconductor memory array of claim 1 , further comprising a control gate insulated from said floating gate or trapping layer by an insulating layer.
8. An integrated circuit comprising:
a semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of at least one row and a plurality of columns or at least one column and a plurality of rows, wherein each of said semiconductor memory cells comprises:
a fin structure extending from a substrate, said fin structure comprising a floating body region configured to be charged to a level indicative of a state of the memory cell to store the state as volatile memory; and
a floating gate or trapping layer insulated from said floating body region and being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory;
wherein when said floating gate or trapping layer of a first memory cell of said plurality of semiconductor memory cells is in a first charge level and said floating gate or trapping layer of a second memory cell of said plurality of semiconductor memory cells is in a second charge level, upon restoration of power to said memory array, said floating body region of said first memory cell is charged to a first charge level as volatile memory and said floating body region of said second memory cell is charged to a second charge level as volatile memory; and
wherein said first and second charge levels as volatile memory are non-algorithmically determined by said first and second charge levels of said floating gate or trapping layer of said first and second memory cells, respectively; and
a control circuit configured to preform said transfer of data stored by the volatile memory and store the data as nonvolatile memory.
9. The integrated circuit of claim 8 , wherein each of said semiconductor memory cells further comprises first and second regions in electrical contact with said floating body region, wherein each of said first and second regions has a conductivity type different from a conductivity type of said floating body region.
10. The integrated circuit of claim 8 , wherein each of said semiconductor memory cells further comprises an isolation layer that isolates said floating body region from said substrate.
11. The integrated circuit of claim 10 , wherein said isolation layer comprises a buried oxide insulating layer.
12. The integrated circuit of claim 10 , wherein said isolation layer comprises a buried layer having a conductivity type different from a conductivity type of said floating body region.
13. The integrated circuit of claim 8 , wherein said floating gate or trapping layer is insulated from said floating body region by an insulating layer.
14. The integrated circuit of claim 8 , wherein each of said semiconductor memory cells further comprises a control gate insulated from said floating gate or trapping layer by an insulating layer.
15. An integrated circuit comprising:
a semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of at least one row and a plurality of columns or at least one column and a plurality of rows, wherein each of said semiconductor memory cells comprises:
a fin structure extending from a substrate, said fin structure comprising a floating body region configured to be charged to a level indicative of a state of the memory cell to store the state as volatile memory; and
a floating gate or trapping layer insulated from said floating body region and being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory;
wherein upon restoration of power to said memory cell, said floating body region stores charge based on nonvolatile memory data stored in said floating gate or trapping layer;
wherein said charge stored in said floating body upon restoration is non-algorithmically determined by said charge stored in said floating gate or trapping layer; and
a control circuit configured to charge said floating body region based on nonvolatile memory data stored in said floating gate or trapping layer.
16. The integrated circuit of claim 15 , wherein each of said semiconductor memory cells further comprises first and second regions in electrical contact with said floating body region, wherein each of said first and second regions has a conductivity type different from a conductivity type of said floating body region.
17. The integrated circuit of claim 15 , wherein each of said semiconductor memory cells further comprises an isolation layer that isolates said floating body region from said substrate.
18. The integrated circuit of claim 17 , wherein said isolation layer comprises a buried layer having a conductivity type different from a conductivity type of said floating body region.
19. The integrated circuit of claim 15 , wherein said floating gate or trapping layer is insulated from said floating body region by an insulating layer.
20. The integrated circuit of claim 15 , wherein each of said semiconductor memory cells further comprises a control gate insulated from said floating gate or trapping layer by an insulating layer.