Semiconductor package having an isolation wall to reduce electromagnetic coupling
A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.
1. A semiconductor device comprising:
a ground plane with a surface and an aperture in the surface;
a first circuit on a first portion of the surface of the ground plane that is located at a first side of the aperture, wherein the first circuit comprises a first plurality of electrical components, including a first transistor, and a first wire bond array electrically coupled between the first transistor and a first lead, wherein the first lead is located at a first side of the device;
a second circuit on a second portion of the ground plane that is located at a second side of the aperture that is opposite the first side, wherein the second circuit comprises a second plurality of electrical components, including a second transistor, and a second wire bond array electrically coupled between the second transistor and a second lead, wherein the second lead is located at the first side of the device; and
an isolation wall formed of electrically conductive material inserted into the aperture between the first circuit and the second circuit and electrically connected to the ground plane, the isolation wall formed of a rectangular body of material that extends perpendicularly from the surface of the ground plane between the first and second wire bond arrays and above a height of the first and second wire bond arrays, the isolation wall being configured to reduce electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.
2. The semiconductor device as recited in claim 1 , wherein the isolation wall is formed from an electrically conductive sheet.
3. The semiconductor device as recited in claim 1 , further comprising:
encapsulation material covering the surface of the ground plane, the first and second transistors, the first and second wire bond arrays, and portions of the first and second leads.
4. The semiconductor device as recited in claim 3 , wherein the isolation wall includes a plurality of holes through which the encapsulation material may flow during a process of making the semiconductor device.
5. The semiconductor device as recited in claim 3 , wherein the encapsulation material has a top surface and a slot extending into the encapsulation material from the top surface to the aperture in the ground plane and between the first circuit and the second circuit, and wherein the isolation wall is located in the slot.
6. The semiconductor device as recited in claim 1 , wherein:
the first plurality of electrical components further includes a first capacitor coupled to the ground plane between the first lead and the first transistor, and a third wire bond array connected between the first capacitor and the first transistor, wherein the first wire bond array is connected between the first lead and the first capacitor.
7. The semiconductor device as recited in claim 6 , wherein:
the second plurality of electrical components further includes a second capacitor coupled to the ground plane between the second lead and the second transistor, and a fourth wire bond array connected between the second capacitor and the second transistor, wherein the second wire bond array is connected between the second lead and the second capacitor.
8. The semiconductor device as recited in claim 7 , wherein:
the third wire bond array is connected between the first capacitor and a gate pad of the first transistor; and
the fourth wire bond array is connected between the second capacitor and a gate pad of the second transistor.
9. The semiconductor device as recited in claim 1 , wherein:
the first plurality of electrical components further comprises a third wire bond array electrically coupled between the first transistor and a third lead, wherein the third lead is located at a second side of the device that is opposite the first side of the device;
the second plurality of electrical components further comprises a fourth wire bond array electrically coupled between the second transistor and a fourth lead, wherein the fourth lead is located at the second side of the device; and
the rectangular body of material extends perpendicularly from the surface of the ground plane between the third and fourth wire bond arrays and above a height of the third and fourth wire bond arrays, and wherein the body of material also extends parallel to the surface of the ground plane between the first and second wire bond arrays, and the third and fourth wire bond arrays.
10. The semiconductor device as recited in claim 9 , wherein the body of material has a first edge and a second edge, wherein the first edge is between the first and second leads, and the second edge is between the third and fourth leads.
11. The semiconductor device as recited in claim 9 , wherein:
the first plurality of electrical components further includes a first capacitor coupled to the ground plane between the first transistor and the third lead, and a third wire bond array connected between the first capacitor and the first transistor, wherein the first capacitor underlies the third wire bond array.
12. The semiconductor device as recited in claim 11 , wherein:
the second plurality of electrical components further includes a second capacitor coupled to the ground plane between the second transistor and the fourth lead, and a fourth wire bond array connected between the second capacitor and the second transistor, wherein the second capacitor underlies the fourth wire bond array.
13. The semiconductor device as recited in claim 12 , wherein:
the third wire bond array is connected between the first capacitor and a drain pad of the first transistor; and
the fourth wire bond array is connected between the second capacitor and a drain pad of the second transistor.
14. The semiconductor device as recited in claim 1 , wherein the first electrical circuit is a carrier amplifier of a Doherty amplifier; and the second electrical circuit is a peaking amplifier of the Doherty amplifier.
15. A Doherty amplifier comprising:
a ground plane with a surface and an aperture in the surface;
a first lead located at a first side of the device and a first side of the aperture;
a second lead located at the first side of the device and a second side of the aperture that is opposite the first side;
a carrier amplifier on a first portion of the ground plane that is located at the first side of the aperture, wherein the carrier amplifier comprises a first plurality of electrical components, including a first transistor, and a first wire bond array electrically coupled between the first transistor and the first lead;
a peaking amplifier on a second portion of the ground plane that is located at the second side of the aperture, wherein the peaking amplifier comprises a second plurality of electrical components, including a second transistor, and a second wire bond array electrically coupled between the second transistor and the second lead; and
an isolation wall formed of electrically conductive material inserted into the aperture between the carrier amplifier and the peaking amplifier and electrically connected to the ground plane, the isolation wall formed of a rectangular body of material that extends perpendicularly from the surface of the ground plane between the first and second wire bond arrays and above a height of the first and second wire bond arrays, the isolation wall being configured to reduce electromagnetic coupling between the carrier amplifier and the peaking amplifier during an operation of at least one of the carrier amplifier and the peaking amplifier.
16. The Doherty amplifier as recited in claim 15 , wherein:
the first plurality of electrical components further includes a first capacitor coupled to the ground plane between the first lead and the first transistor, and a third wire bond array connected between the first capacitor and the first transistor, wherein the first wire bond array is connected between the first lead and the first capacitor.
17. The Doherty amplifier as recited in claim 16 , wherein:
the second plurality of electrical components further includes a second capacitor coupled to the ground plane between the second lead and the second transistor, and a fourth wire bond array connected between the second capacitor and the second transistor, wherein the second wire bond array is connected between the second lead and the second capacitor.
18. The Doherty amplifier as recited in claim 17 , wherein:
the third wire bond array is connected between the first capacitor and a gate pad of the first transistor; and
the fourth wire bond array is connected between the second capacitor and a gate pad of the second transistor.
19. The Doherty amplifier as recited in claim 15 , further comprising:
a third lead located at a second side of the device that is opposite the first side of the device, and located at the first side of the aperture;
a fourth lead located at the second side of the device and the second side of the aperture;
wherein the first plurality of electrical components further comprises a third wire bond array electrically coupled between the first transistor and the third lead; and
wherein the second plurality of electrical components further comprises a fourth wire bond array electrically coupled between the second transistor and the fourth lead, and
wherein the rectangular body of material extends perpendicularly from the surface of the ground plane between the third and fourth wire bond arrays and above a height of the third and fourth wire bond arrays, and wherein the body of material also extends parallel to the surface of the ground plane between the first and second wire bond arrays, and the third and fourth wire bond arrays.
20. The Doherty amplifier as recited in claim 19 , wherein:
the first plurality of electrical components further includes a first capacitor coupled to the ground plane between the first transistor and the third lead, and a third wire bond array connected between the first capacitor and a drain pad of the first transistor, wherein the first capacitor underlies the third wire bond array; and
the second plurality of electrical components further includes a second capacitor coupled to the ground plane between the second transistor and the fourth lead, and a fourth wire bond array connected between the second capacitor and a drain pad of the second transistor, wherein the second capacitor underlies the fourth wire bond array.