Planarization and flip-chip fabrication process of fine-line-geometry features with high-roughness metal-alloyed surfaces

1. A method of semiconductor device fabrication that enables fine-line geometry lithographic definition and small form-factor packaging comprising:

forming contacts on a metal layer of the semiconductor device;

applying a protective mask layer over active regions and surfaces of the contacts having rough surface morphology;

planarizing a surface of the semiconductor device until the protective mask layer is removed and the surfaces of the contacts having rough surface morphology are planarized;

applying a resist layer over the surface of the semiconductor device where the protective mask layer is removed and the surfaces of the contacts having rough surface morphology after planarizing;

lithography of fine line gate features on the resist layer; and

forming contact stacks on the surfaces of the contacts which are planarized.

2. The method of claim 1 , wherein planarizing the protective mask layer comprises chemical-mechanical polishing (CMP) the protective mask layer until the protective mask layer is removed and the surfaces of the contacts which are planarized.

3. The method of claim 1 , wherein planarizing the protective mask layer comprises grinding the protective mask layer until the protective mask layer is removed and the surfaces of the contacts which are planarized.

4. The method of claim 1 , wherein applying a protective mask layer comprises applying the protective mask in a thickness of 0.05 to 0.2 micron range.

5. The method of claim 1 , wherein applying a protective mask layer comprises applying the protective mask layer in a thickness of 0.05 to 0.2 micron range, the thickness of the protective mask layer being approximately 50% of a thickness of the contacts.

6. The method of claim 2 , wherein planarizing the protective mask layer with chemical-mechanical polishing (CMP) comprises polishing with a chemical and physical slurry, the chemical and physical slurry comprises at least one of elements that chemically remove materials of the protective mask layer and an abrasive that physically removes the materials of the protective mask and elements that chemically remove materials of the contacts and an abrasive that physically removes the materials of the contacts.

7. The method of claim 6 , wherein the chemical and physical slurry has abrasives having a granular size of less than one tenth of a metal thickness of the contacts.

8. The method of claim 1 , comprising:

applying a solvent to the resist layer to expose a surface area between the contacts; and

forming the gate terminal in the surface area exposed between the contacts.

9. The method of claim 1 , comprising forming a solder bump on each of the contact stacks.

10. A method of semiconductor device fabrication that enables fine-line geometry lithographic definition and small form-factor packaging comprising:

forming contacts on a metal layer of the semiconductor device;

applying a protective mask layer over active regions and surfaces of the contacts having rough surface morphology, wherein the protective mask has a thickness in a range of 0.05 to 0.2 micron range;

planarizing a surface of the semiconductor device until the protective mask layer is removed and the surfaces of the contacts having rough surface morphology are planarized;

applying a resist layer over the surface of the semiconductor device where the protective mask layer is removed and the surfaces of the contacts having rough surface morphology are planarized;

lithography of fine line gate features on the resist layer in a surface area between the contacts after planarizing the surface of the semiconductor device;

forming the gate terminal in the surface area exposed between the contacts after planarizing the surface of the semiconductor device; and

forming contact stacks on the surfaces of the contacts which are planarized.

11. The method of claim 10 , wherein planarizing the protective mask layer comprises chemical-mechanical polishing (CMP) the protective mask layer until the protective mask layer is removed and the surfaces of the contacts which are planarized.

12. The method of claim 10 , wherein planarizing the protective mask layer comprises grinding the protective mask layer until the protective mask layer is removed and the surfaces of the contacts which are planarized.

13. The method of claim 10 , wherein the thickness of the protective mask layer is approximately 50% of a thickness of the contacts.

14. The method of claim 11 , wherein planarizing the protective mask layer with chemical-mechanical polishing (CMP) comprises polishing with a chemical and physical slurry, the chemical and physical slurry comprises at least one of elements that chemically remove materials of the protective mask layer and an abrasive that physically removes the materials of the protective mask and elements that chemically remove materials of the contacts and an abrasive that physically removes the materials of the contacts.

15. The method of claim 14 , wherein the chemical and physical slurry has abrasives having a granular size of less than one tenth of a metal thickness of the contacts.

16. The method of claim 10 , comprising forming a solder bump on each of the contact stacks.

17. A method of semiconductor device fabrication that enables fine-line geometry lithographic definition and small form-factor packaging comprising:

forming contacts on a metal layer of the semiconductor device;

applying a protective mask layer over active regions and surfaces of the contacts having rough surface morphology, wherein the protective mask has a thickness in a range of 0.05 to 0.2 micron range, wherein the thickness of the protective mask layer is approximately 50% of a thickness of the contacts;

planarizing a surface of the semiconductor device until the protective mask layer is removed and the surfaces of the contacts having rough surface morphology are planarized;

applying a resist layer over the surface of the semiconductor device where the protective mask layer is removed and the surfaces of the contacts having rough surface morphology are planarized;

lithography of fine line gate features on the resist layer in a surface area between the contacts after planarizing the surface of the semiconductor device;

forming the gate terminal in the surface area exposed between the contacts after planarizing the surface of the semiconductor device;

forming solder bump bases on the surfaces of the contacts which are planarized; and

forming a solder bump on each of each of the solder bump bases.

18. The method of claim 17 , wherein planarizing the protective mask layer comprises chemical-mechanical polishing (CMP) the protective mask layer until the protective mask layer is removed and the surfaces of the contacts which are planarized, wherein planarizing the protective mask layer with chemical-mechanical polishing (CMP) comprises polishing with a chemical and physical slurry, the chemical and physical slurry comprises at least one of elements that chemically remove materials of the protective mask layer and an abrasive that physically removes the materials of the protective mask and elements that chemically remove materials of the contacts and an abrasive that physically removes the materials of the contacts.

19. The method of claim 18 , wherein the chemical and physical slurry has abrasives having a granular size of less than one tenth of a metal thickness of the contacts.

20. The method of claim 17 , wherein planarizing the protective mask layer comprises grinding the protective mask layer until the protective mask layer is removed and the surfaces of the contacts which are planarized.