Power converter

1. A power converter, comprising:

a switched-capacitor conversion circuit configure to receive an input voltage, and operate, according to a first operating frequency, to convert the input voltage into an intermediate voltage; and

an inductor buck circuit connected in series to the switched-capacitor conversion circuit, and configured to receive the intermediate voltage and operated with a second operating frequency to generate an output voltage on a conversion output terminal according to the intermediate voltage,

wherein the switched-capacitor conversion circuit comprises a plurality of switches, and the inductor buck circuit comprises a high-side switch and an inductor connected in series between the switched-capacitor conversion circuit and the conversion output terminal,

wherein during a period in which the high-side switch is turned on, all of the plurality of switches of the switched-capacitor conversion circuit are switched according to the first operating frequency; and

wherein all of the plurality of switches are used in power conversion of the switched-capacitor conversion circuit.

2. The power converter according to claim 1 , wherein the plurality of switches are switched according to a clock signal having the first operating frequency, and the high-side switch of the inductor buck circuit is controlled by a first switching signal having the second operating frequency, and

wherein the power converter comprises a clock generator configured to receive the first switching signal, and generate the clock signal according to the first switching signal.

3. The power converter according to claim 2 , wherein the clock generator comprises:

a frequency detection circuit configured to receive the first switching signal, and detect a frequency of the first switching signal, to generate a frequency signal;

a phase detection circuit configured to receive the first switching signal and the frequency signal, and generate a detection signal, wherein when the first switching signal and the frequency signal are in phase, the phase detection circuit enables the enable signal; and

a frequency divider circuit configured to receive the detection signal, and generate the clock signal according to the detection signal.

4. The power converter according to claim 3 , wherein the first operating frequency of the clock signal is a half of a frequency of the detection signal.

5. The power converter according to claim 3 , wherein the frequency detection circuit comprises:

a current source configured to provide a charging current;

a first switch coupled between the current source and a first node, and controlled by the first operating signal;

a capacitor coupled between the first node and a second node, wherein a ramp voltage is generated on the first node, and the frequency detection circuit receives the output voltage through the second node;

a second switch coupled between the first node and the second node; and

a comparator having a positive input coupled to the first node, and a negative input receiving the intermediate voltage, and configured to compare the ramp voltage and the intermediate voltage, to generate the frequency signal.

6. The power converter according to claim 3 , wherein the phase detection circuit comprises:

a D-Flip-Flop having an input terminal receiving the detection signal, a clock terminal receiving the first switching signal, and an output terminal generating the detection signal.

7. The power converter according to claim 3 , wherein the frequency divider circuit comprises:

a D-Flip-Flop having an input terminal, a clock terminal receiving the detection signal, an output terminal generating the clock signal, and an inverting output terminal.

8. The power converter according to claim 1 , wherein the input terminal of the inductor buck circuit receives the intermediate voltage, and the inductor buck circuit comprises:

an input capacitor coupled between an input terminal of the inductor buck circuit and ground;

a high-side switch coupled between the input terminal of the inductor buck circuit and a first node;

a low-side switch coupled between the first node and ground;

an inductor coupled between the first node and the conversion output terminal; and

an output capacitor coupled between the conversion output terminal and ground,

wherein a turn-on period of the high-side switch and a turn-on period of the low-side switch do not overlap with each other.