IP Library › Granted Patent US 10,795,811
Granted Patent B2
US 10,795,811 · App. 16/596,703 · Granted Oct 6, 2020

Method for managing a memory apparatus

Inventors: Tsai-Cheng Lin (Hsinchu, TW); Chun-Kun Lee (Hsinchu County, TW)
Assignee: Silicon Motion, Inc.
G06F12/0246G06F12/1009G06F2212/7207G06F2212/7208G06F2212/7209
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Quick Facts
Patent No.
US 10,795,811
App. No.
16/596,703
Granted
Oct 6, 2020
Kind
B2
Abstract

A method for managing a memory apparatus including at least one non-volatile (NV) memory element including a plurality of physical blocks includes: obtaining a first host address and first data from a received first access command; obtaining a second host address and second data from a received second access command; linking the first host address to at least a first page of the physical block and linking the second host address to at least a second page of the physical block; storing the first data and second data into the physical block; and selectively erasing a portion of the physical block according to a valid/invalid page count of the physical block, the valid/invalid page count corresponding to accessing pages of the physical block. A difference value of the first host address and the second host address is greater than a number of pages of the physical block.

Claims (14)

1. A method for managing a memory apparatus, the memory apparatus comprising at least one non-volatile (NV) memory element comprising a plurality of physical blocks, the method comprising:

obtaining a first host address and first data from a received first access command;

obtaining a second host address and second data from a received second access command;

linking the first host address to at least a first page of a physical block of the plurality of physical blocks and linking the second host address to at least a second page of the physical block;

storing the first data and second data into the physical block; and

selectively erasing a portion of the plurality of physical blocks according to a valid/invalid page count of each physical block of the plurality of physical blocks, the valid/invalid page count corresponding to accessing pages of the plurality of physical blocks;

wherein a difference value of the first host address and the second host address is greater than a number of pages of the physical block.

2. A method for managing a memory apparatus, the memory apparatus comprising at least one non-volatile (NV) memory element, each of which comprises a plurality of physical blocks, the method comprising:

obtaining a first host address and first data from a received first access command;

obtaining a second host address and second data from a received second access command;

linking the first host address to at least a page of a first physical block of the plurality of physical blocks, and linking the second host address to at least a page of a second physical block of the plurality of physical blocks that is different from the first physical block; and

selectively erasing a portion of the plurality of physical blocks according to a valid/invalid page count of each physical block of the plurality of physical blocks, the valid/invalid page count corresponding to accessing pages of the plurality of physical blocks;

wherein a difference value of the first host address and the second host address is smaller than a number of pages of each physical block.

3. The method of claim 2 , wherein the first host address is linked to at least a first page of the first physical block, and the second host address is linked to at least a second page of the second physical block.

Continuity (7)
Continuation 15642295 · Jul 5, 2017
Continuation 14566724 · Dec 11, 2014
Continuation 13604644 · Sep 6, 2012
Continuation 12471462 · May 25, 2009
Provisional Application 61140850 · Dec 24, 2008
Provisional Application 61112173 · Nov 6, 2008
Related Publication 20200042437A1 · Feb 6, 2020
Cited By (1)
US 12,292,826