Systems and methods for providing an interface on a printed circuit board using pin solder enhancement

1. A method for applying solder to a pin, comprising:

disposing a given amount of solder on a non-wetable surface of a planar substrate;

aligning the pin with the solder disposed on the non-wetable surface of the planar substrate;

inserting the pin in the solder;

performing a reflow process to cause the solder to transfer from the planar substrate to the pin without soldering the pin to the planar substrate; and

moving the pin, with the solder applied thereto, away from the planar substrate.

2. The method according to claim 1 , wherein the given amount of solder is determined in accordance with the following Mathematical Equation: S=(v c +v f −v p )·2, where S represents an amount of solder to be applied to the planar substrate, v c represents a volume of a plated cavity to be formed or already formed in a circuit board, v f represents a volume of a fillet of a solder joint to be formed between the pin and the circuit board, and v p represents a volume of the pin.

3. The method according to claim 1 , wherein the planar substrate comprises a fiberglass laminate material, a ceramic material, or tempered glass.

4. The method according to claim 1 , wherein the planar substrate has a thickness selected so that the planar substrate remains planar throughout the reflow process.

5. The method according to claim 1 , further comprising, subsequent to when the pin is moved away from the planar substrate, using the solder to create a soldered interface between a circuit board and the pin, where the circuit board is separate and apart from the planar substrate.

6. The method according to claim 5 , wherein the circuit board comprises:

a core substrate comprising a plurality of laminated dielectric substrate layers with a first via formed therethrough,

a first trace disposed on an exposed surface of the core substrate that is in electrical contact with the first via,

a first High Density Interconnect (“HDI”) substrate laminated to the core substrate such that the first trace electrically connects the first via with a second via formed through the first HDI substrate,

a second trace disposed on an exposed surface of the first HDI substrate that is in electrical contact with the second via, and

a second HDI substrate laminated to the first HDI substrate such that the second trace electrically connects the second via to a third via formed through the second HDI substrate;

wherein the second via comprises a buried via with a central axis spatially offset from central axis of the first and third vias, and the first and second vias having diameters which are smaller than a diameter of the third via.

7. The method according to claim 6 , wherein the third via comprises the plated contact cavity.

8. The method according to claim 6 , wherein the central axis of the first via is aligned with the central axis of the third via, and the central axis of the second via is horizontally offset from the central axis of the first and third vias.

9. The method according to claim 6 , wherein the diameter of the second via is smaller than the diameter of the first via.