Error cache segmentation for power reduction
A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. Also, the cache memory is divided into a plurality of segments, wherein each segment of the cache memory is direct mapped to a corresponding segment of the memory bank, wherein an address of each of the second plurality of data words is mapped to a corresponding segment in the cache memory, and wherein data words from a particular segment of the memory bank only get stored in a corresponding direct mapped segment of the cache memory.
1. A memory device for storing data, the memory device comprising:
a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments;
a pipeline configured to process write operations of a first plurality of data words addressed to the memory bank; and
a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the second plurality of data words are a subset of the first plurality of data words, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank, wherein the cache memory is divided into a plurality of segments, wherein each segment of the cache memory is direct mapped to a corresponding segment of the memory bank, wherein an address of each of the second plurality of data words is mapped to a corresponding segment in the cache memory, and wherein data words from a particular segment of the memory bank only get stored in a corresponding direct mapped segment of the cache memory.
2. The memory device of claim 1 , wherein each segment of the cache memory is associated with a respective counter to keep track of a number of valid entries within each segment.
3. The memory device of claim 1 , wherein each segment of the cache memory is associated with two respective counters to keep track of a number of valid entries corresponding to write 1 errors and a number of valid entries corresponding to write 0 errors within each segment.
4. The memory device of claim 1 , wherein a direct mapping between the plurality of segments of the cache memory and the plurality of segments of the memory bank comprise a logical mapping.
5. The memory device of claim 1 , wherein a direct mapping between the plurality of segments of the cache memory and the plurality of segments of the memory bank comprise a physical mapping.
6. The memory device of claim 1 , wherein the memory bank comprises a plurality of magnetic random access memory (MRAM) cells.
7. The memory device of claim 1 , wherein the memory bank comprises a plurality of spin-transfer torque magnetic random access memory (STT-MRAM) cells.
8. A memory device for storing data, the memory device comprising:
a plurality of memory banks, each comprising a plurality of addressable memory cells, wherein each of the plurality of memory banks is divided into a plurality of segments;
a pipeline configured to process write operations of a first plurality of data words addressed to the plurality of memory banks; and
a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the second plurality of data words are a subset of the first plurality of data words, wherein the cache memory is associated with the plurality of memory banks and wherein further each data word of the second plurality of data words is either awaiting write verification associated with a bank from the plurality of memory banks or is to be re-written into a bank from the plurality of memory banks, wherein the cache memory is divided into a plurality of segments, wherein each segment of the cache memory is direct mapped to a corresponding segment of a memory bank of the plurality of memory banks, and wherein an address of each of the second plurality of data words is mapped to a corresponding segment in the cache memory.
9. The memory device of claim 8 , wherein each segment of the cache memory is associated with a respective counter to keep track of a number of valid entries within each segment.
10. The memory device of claim 8 , wherein each segment of the cache memory is associated with two respective counters to keep track of a number of valid entries corresponding to write 1 errors and a number of valid entries corresponding to write 0 errors within each segment.
11. The memory device of claim 8 , wherein a direct mapping between the plurality of segments of the cache memory and the plurality of segments of the memory bank comprise a logical mapping.
12. The memory device of claim 8 , wherein a direct mapping between the plurality of segments of the cache memory and the plurality of segments of the memory bank comprise a physical mapping.
13. The memory device of claim 8 , wherein data words from a particular segment of the memory bank only get stored in a corresponding direct mapped segment of the cache memory.
14. The memory device of claim 8 , wherein the memory bank comprises a plurality of spin-transfer torque magnetic random access memory (STT-MRAM) cells.
15. A memory device comprising:
a memory bank comprising a plurality of magnetic random access memory (MRAM) cells, wherein each memory cell is configured to store a data word at a respective one of a plurality of memory addresses, and wherein the memory bank is divided into a plurality of segments;
a dynamic redundancy register comprising data storage elements, wherein the dynamic redundancy register is divided into a plurality of segments, wherein each segment of the dynamic redundancy register is mapped to a corresponding segment of the memory bank; and
a pipeline bank coupled to the memory bank and the dynamic redundancy register, wherein the pipeline bank is configured to:
write a data word into a segment of the memory bank that corresponds to a selected address of the plurality of memory addresses;
verify the data word written into the memory bank to determine whether the data word was successfully written; and
responsive to a determination that the data word was not successfully written, writing the data word and the selected address into a segment of the dynamic redundancy register that directly maps to the segment of the memory bank associated with the write, wherein data words from a particular segment of the memory bank get stored in a corresponding mapped segment of the dynamic redundancy register.
16. The memory device of claim 15 , wherein each segment of the dynamic redundancy register is associated with a respective counter to keep track of a number of valid entries within each segment.
17. The memory device of claim 15 , wherein each segment of the dynamic redundancy register is associated with two respective counters to keep track of a number of valid entries corresponding to write 1 errors and a number of entries corresponding to write 0 errors within each segment.
18. The memory device of claim 15 , wherein each segment of the dynamic redundancy register is direct mapped to a corresponding segment of the memory bank.
19. The memory device of claim 15 , wherein each segment of the dynamic redundancy register is mapped to a corresponding segment of the memory bank using non-direct mapping and wherein the non-direct mapping is performed using a mapping table.
20. The memory device of claim 15 , wherein the plurality of segments are of non-uniform sizes.