IP Library Granted Patent US 11,156,979
Granted Patent B2
US 11,156,979 · App. 16/600,937 · Granted Oct 26, 2021

System and method of packet acknowledgment in a wireless communication system

Inventors: Dan Wolberg (Yanuv, IL); Ofer Blonskey (Even Yehuda, IL); Ofri Olinky (Ra'anana, IL); David Marks (Ra'anana, IL); Omer Ephrat (Ramat Gan, IL); Nir Efraim Joseph Tal (Haifa, IL)
Assignee: Coretigo, Ltd.
G05B19/052G05B19/4185H04B1/713H04B1/7136H04B1/7143H04L1/0061H04L1/0083H04L1/203H04L5/0055H04L47/2466H04L47/6215H04W28/0268H04W28/04G05B2219/15117H04B2001/71362H04W84/20
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Quick Facts
Patent No.
US 11,156,979
App. No.
16/600,937
Granted
Oct 26, 2021
Kind
B2
Abstract

A novel and useful acknowledgement and adaptive frequency hopping mechanism for use in wireless communication systems such as IO-Link Wireless. One or two additional acknowledgement bits are added to packet transmissions. One is a current acknowledgment bit which indicates whether a packet was successfully received anytime during the current cycle. The second bit is a previous acknowledgment bit which indicates whether packets were received successfully anytime during the previous cycle. An adaptive hopping table is constructed using a greedy algorithm which chooses frequencies with the best PER for transmission of higher priority packets, while equalizing the PER products across cycles. A last resort frequency mechanism further improves transmission success by switching to a better performing channel for the last subcycle when previous attempts to transmit a high priority packet have failed.

Claims (9)

1. A method of reliable uplink communications between a master and multiple devices in a wireless communications network, comprising:

resetting, on said master, a current acknowledgement bit at a beginning of each cycle, each cycle consisting of a plurality of subcycles;

receiving a packet from a device over a wireless link;

setting said current acknowledgement bit for the duration of a cycle in response to successful reception of said packet from said device within said cycle;

transmitting the state of said current acknowledgement bit to said device each subcycle; and

keeping said current acknowledgement bit set for a remainder of said cycle regardless of whether subsequent packets are successfully received within said cycle.

2. The method according to claim 1 , further comprising transmitting an ACK or NACK from said master to said device indicating whether the packet sent during a previous subcycle was successfully received or not successfully received, respectively, by said master.

3. The method according to claim 1 , further comprising setting a state of a previous acknowledgement bit to the state of said current acknowledgement bit at the beginning of each cycle and transmitting said previous acknowledgement bit to said device each subcycle.

4. The method according to claim 3 , further comprising declaring, by said device, successful receipt of a packet transmitted during a previous cycle if said previous acknowledgement bit receiving during a current cycle is set.

Assignments (3)
SECURITY INTEREST Recorded Sep 16, 2025
From: CORETIGO LTD.
To: BANK HAPOALIM B.M.
Reel/Frame 072272/0541 →
SECURITY INTEREST Recorded Jan 11, 2023
From: CORETIGO LTD.
To: SILICON VALLEY BANK
Reel/Frame 062348/0391 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2019
From: WOLBERG, DAN; BLONSKEY, OFER; OLINKY, OFRI; MARKS, DAVID; EPHRAT, OMER; TAL, NIR EFRAIM JOSEPH
To: CORETIGO LTD.
Reel/Frame 050808/0707 →
Continuity (3)
Provisional Application 62745685 · Oct 15, 2018
Provisional Application 62870273 · Jul 3, 2019
Related Publication 20200119885A1 · Apr 16, 2020