CoWos interposer with selectable/programmable capacitance arrays

1. An interposer circuit, comprising:

a substrate;

a dielectric layer disposed on top of the substrate;

two or more connection layers including a first connection layer and a second connection layer disposed at different depths in the dielectric layer, wherein a fuse is disposed in the first connection layer, and wherein the first connection layer is coupled to a first power node and the second connection layer is coupled to a first ground node;

a first capacitor in series with the fuse and connected between the first and the second connection layers; and

first, second, and third micro-bumps on top of the dielectric layer, wherein the fuse is coupled between the first and second micro-bumps and the first capacitor is coupled between the second and third micro-bumps, wherein the first and second micro-bumps are coupled to a power supply to provide a current to the fuse.

2. The interposer circuit of claim 1 , further comprising:

a test circuit configured to electrically couple to the second and third micro-bumps and to test a leakage current of the first capacitor.

3. The interposer circuit of claim 2 , wherein the test circuit is configured to couple to the first and second micro-bumps to induce a first current in the fuse to blow the fuse.

4. The interposer circuit of claim 1 , wherein the fuse is an e-fuse, and wherein the e-fuse is disconnected by applying a first voltage between the first and second micro-bumps and wherein the e-fuse is connected by applying a second voltage between the first and second micro-bumps.

5. The interposer circuit of claim 1 , further comprising:

two or more through-silicon vias in the substrate to provide electrical connection between the two or more connection layers and a voltage source, and wherein the voltage source is coupled to the two or more through-silicon vias via at least two solder-bumps that are coupled to the through-silicon vias at a bottom of the substrate.

6. The interposer circuit of claim 5 , wherein a second power node of the voltage source is electrically connected to the first power node via one or more through-silicon vias and the two or more connection layers, wherein a second ground node of the voltage source is electrically connected to first ground node via the one or more through-silicon vias and the two or more connection layers.

7. The interposer circuit of claim 1 , wherein the first capacitor is a metal-insulator-metal (MiM) capacitor or a metal-oxide-metal (MoM) capacitor.

8. A chip on wafer on substrate (CoWoS) circuit, comprising:

a system on a chip (SOC) attached to an upper surface of an interposer,

the interposer comprises one or more receiving locations at the upper surface,

wherein the SOC is installed in a receiving location; and

a substrate attached to lower surface of the interposer,

wherein each receiving location of the interposer includes a circuit therein having one or more combinations of a programmable e-fuse connected in series with an associated capacitor, and

wherein the programmable e-fuse is configured to be turned off if the associated capacitor of the programmable e-fuse is defective, wherein each one of the one or more receiving locations comprises first, second, and third micro-bumps on the upper surface of the interposer, wherein the programmable e-fuse is coupled between the first and second micro-bumps and the associated capacitor is coupled between the second and third micro-bumps, and wherein the first and second micro-bumps are coupled to a power supply to provide current to the programmable e-fuse.

9. The CoWoS circuit of claim 8 , wherein a test circuit is configured to blow the programmable e-fuse if the associated capacitor is defective.

10. The CoWoS circuit of claim 9 , wherein the test circuit is configured to determine a leakage current of the associated capacitor to determine, based on the leakage current, if the associated capacitor is defective.

11. The CoWoS circuit of claim 8 , wherein the associated capacitor is a metal-insulator-metal (MiM) or metal-oxide-metal (MoM) capacitor.

12. The CoWoS circuit of claim 8 , wherein each receiving location of the interposer includes four circuits therein each having a combination of a programmable e-fuse connected in series with a capacitor.

13. The CoWoS circuit of claim 12 , wherein the SOC is attached to the four circuits and associated capacitors of the four circuits, wherein when a capacitor is defective the programmable e-fuse associated with the capacitor is blown and the defective capacitor is disconnected.

14. The CoWoS circuit of claim 13 , wherein a power connection is provided by the substrate through the interposer to the SOC and wherein the four circuits are connected in parallel across a power node and a ground node of the power connection.

15. An interposer circuit, comprising:

a substrate;

a dielectric layer disposed on top of the substrate;

two or more connection layers including a first connection layer and a second connection layer disposed at different depths in the dielectric layer, wherein a fuse is disposed in the first connection layer, and wherein the first connection layer is coupled to a power node and the second connection layer is coupled to a ground node;

a first capacitor in series with the fuse and connected between the first and the second connection layers;

first, second, and third micro-bumps on top of the dielectric layer, wherein the fuse is coupled between the first and second micro-bumps and the first capacitor is coupled between the second and third micro-bumps;

first and second solder-bumps at a bottom of the substrate, wherein the first solder-bump is coupled to the power node and the second solder-bump is coupled to the ground node; and

a test circuit.

16. The interposer circuit of claim 15 , wherein:

the test circuit is electrically coupled between the second and third micro-bumps to measure a leakage current of the first capacitor.

17. The interposer circuit of claim 15 , wherein the test circuit is electrically coupled between the first and second micro-bumps to supply a first current through the fuse, and wherein the first current is above a current threshold that is configured to blow the fuse.

18. The interposer circuit of claim 15 , further comprising:

a system-on-chip configured to be disposed on top of the dielectric layer and to electrically couple to the power node and the ground node via the first micro-bump and the third micro-bump.

19. The interposer circuit of claim 15 , wherein the interposer circuit is an interface circuit.

20. The interposer circuit of claim 15 , wherein the fuse is an e-fuse, wherein the test circuit is electrically coupled between the first and second micro-bumps, and wherein the test circuit is configured to apply a first voltage between the first and second micro-bumps to disconnect the e-fuse and to apply a second voltage between the first and second micro-bumps to connect the e-fuse.