Uniform layouts for SRAM and register file bit cells
Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.
1. An integrated circuit structure, comprising:
a substrate;
a six transistor (6T) static random access memory (SRAM) bit cell on the substrate, the 6T SRAM bit cell comprising:
first and second active regions parallel along a first direction of the substrate; and
first, second, third and fourth gate lines over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction, wherein all of the first, second, third and fourth gate lines vertically overlap one of the first active region or the second active region, and wherein at least two of the first, second, third or fourth gate lines vertically overlap both of the first active region and the second active region.
2. The integrated circuit structure of claim 1 , wherein the first active region is an N-type doped active region, and the second active region is a P-type doped active region.
3. The integrated circuit structure of claim 1 , wherein the first and second active regions are in first and second silicon fins, respectively.
4. The integrated circuit structure of claim 1 , wherein all individual ones of the first, second, third and fourth gate lines are continuous between the first and second active regions.
5. The integrated circuit structure of claim 1 , wherein the 6T SRAM bit cell has a first length along the first direction and a second length along the second direction, and the first length is greater than the second length.
6. The integrated circuit structure of claim 1 , wherein individual ones of the first, second, third and fourth gate lines are spaced apart from one another by trench contact lines parallel along the second direction of the substrate.
7. An integrated circuit structure, comprising:
a substrate;
a six transistor (6T) static random access memory (SRAM) bit cell on the substrate, the 6T SRAM bit cell comprising:
first and second active regions parallel along a first direction of the substrate, wherein the first active region is an N-type doped active region, and the second active region is a P-type doped active region; and
first, second, third and fourth gate lines over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction, wherein all of the first, second, third and fourth gate lines vertically overlap one of the first active region or the second active region.
8. An integrated circuit structure, comprising:
a substrate;
a six transistor (6T) static random access memory (SRAM) bit cell on the substrate, the 6T SRAM bit cell comprising:
first and second active regions parallel along a first direction of the substrate;
and first, second, third and fourth gate lines over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction, wherein all of the first, second, third and fourth gate lines vertically overlap one of the first active region or the second active region;
wherein each of the first, second, third, and fourth gate lines vertically overlap the first active region.