OR logic operation circuit and driving method, shift register unit, gate drive circuit, and display device
An OR logic operation circuit and a driving method, a shift register unit, a gate drive circuit, and a display device are provided. The OR logic operation circuit includes: a first inverter, a second inverter, a first control circuit, and a second control circuit. The first inverter is configured to invert a first control signal, which is received, to output a second control signal; the second inverter is configured to invert a third control signal received to output a fourth control signal; the first control circuit is configured to perform first control on a first node and the output terminal to achieve an OR operation and output a first level of an output signal at the output terminal; and the second control circuit is configured to perform second control on the first node and the output terminal to output a second level of the output signal at the output terminal.
1. A shift register unit, comprising a first shift register sub-unit, a second shift register sub-unit, and an OR logic operation circuit,
wherein the OR logic operation circuit comprises:
a first inverter, wherein the first inverter is configured to invert a first control signal, which is received, to output a second control signal;
a second inverter, wherein the second inverter is configured to invert a third control signal, which is received, to output a fourth control signal;
a first control circuit, wherein the first control circuit is connected to the first inverter, the second inverter, and an output terminal, and is configured to perform first control on a first node and the output terminal to achieve an OR operation, under control of the second control signal and the fourth control signal, and to output a first level of an output signal at the output terminal; and
a second control circuit, wherein the second control circuit is connected to the output terminal, and is configured to perform second control on the first node and the output terminal to output a second level of the output signal at the output terminal,
wherein the first shift register sub-unit is connected to the first inverter of the OR logic operation circuit, and the second shift register sub-unit is connected to the second inverter of the OR logic operation circuit.
2. The shift register unit according to claim 1 , wherein the second control circuit comprises:
a first transistor, wherein a first terminal of the first transistor is connected to a control terminal of the first transistor, and is connected to a first voltage terminal to receive a first voltage;
a second transistor, wherein a first terminal of the second transistor is connected to the first voltage terminal to receive the first voltage, a control terminal of the second transistor is connected to a second terminal of the first transistor and the first node; and
a first capacitor, wherein one terminal of the first capacitor is connected to the first node, and another terminal of the first capacitor is connected to a second terminal of the second transistor and the output terminal.
3. The shift register unit according to claim 2 , wherein the first control circuit comprises:
a third transistor, wherein a first terminal of the third transistor is connected to the first node, and a control terminal of the third transistor is connected to a third node to receive the fourth control signal;
a fourth transistor, wherein a first terminal of the fourth transistor is connected to a second terminal of the third transistor, a control terminal of the fourth transistor is connected to a second node to receive the second control signal, and a second terminal of the fourth transistor is connected to a second voltage terminal to receive a second voltage;
a fifth transistor, wherein a first terminal of the fifth transistor is connected to the output terminal, and a control terminal of the fifth transistor is connected to the control terminal of the third transistor; and
a sixth transistor, wherein a first terminal of the sixth transistor is connected to a second terminal of the fifth transistor, a control terminal of the sixth transistor is connected to the control terminal of the fourth transistor, and a second terminal of the sixth transistor is connected to the second voltage terminal to receive the second voltage.
4. The shift register unit according to claim 3 , wherein the first transistor to the sixth transistor all are depletion mode transistors.
5. The shift register unit according to claim 4 , wherein the first inverter comprises:
a seventh transistor, wherein a first terminal of the seventh transistor is connected to a control terminal of the seventh transistor, and is connected to the first voltage terminal to receive the first voltage; and
an eighth transistor, wherein a first terminal of the eighth transistor is connected to a second terminal of the seventh transistor and a second node, a control terminal of the eighth transistor, as an input terminal of the first inverter, receives the first control signal, and a second terminal of the eighth transistor is connected to the second voltage terminal to receive the second voltage,
wherein the second node serves as an output terminal of the first inverter.
6. The shift register unit according to claim 5 , wherein the second inverter comprises:
a ninth transistor, wherein a first terminal of the ninth transistor is connected to a control terminal of the ninth transistor, and is connected to the first voltage terminal to receive the first voltage; and
a tenth transistor, wherein a first terminal of the tenth transistor is connected to a second terminal of the ninth transistor and a third node, and a control terminal of the tenth transistor, as an input terminal of the second inverter, receives the third control signal, and a second terminal of the tenth transistor is connected to the second voltage terminal to receive the second voltage,
wherein the third node serves as an output terminal of the second inverter.
7. The shift register unit according to claim 1 , wherein the first inverter comprises:
a seventh transistor, wherein a first terminal of the seventh transistor is connected to a control terminal of the seventh transistor, and is connected to a first voltage terminal to receive a first voltage; and
an eighth transistor, wherein a first terminal of the eighth transistor is connected to a second terminal of the seventh transistor and a second node, a control terminal of the eighth transistor, as an input terminal of the first inverter, receives the first control signal, and a second terminal of the eighth transistor is connected to a second voltage terminal to receive a second voltage,
wherein the second node serves as an output terminal of the first inverter.
8. The shift register unit according to claim 1 , wherein the second inverter comprises:
a ninth transistor, wherein a first terminal of the ninth transistor is connected to a control terminal of the ninth transistor, and is connected to a first voltage terminal to receive a first voltage; and
a tenth transistor, wherein a first terminal of the tenth transistor is connected to a second terminal of the ninth transistor and a third node, and a control terminal of the tenth transistor, as an input terminal of the second inverter, receives the third control signal, and a second terminal of the tenth transistor is connected to a second voltage terminal to receive a second voltage,
wherein the third node serves as an output terminal of the second inverter.
9. The shift register unit according to claim 1 , wherein the first shift register sub-unit comprises a first input circuit, a first output circuit, and a first noise reduction circuit,
wherein the first input circuit is connected to a first control node, and is configured to control a level of the first control node, in response to a first input signal, to obtain the first control signal;
the first output circuit is connected to the first control node and a first shift output terminal, and is configured to output a first shift output signal at the first shift output terminal under control of the first control signal; and
the first noise reduction circuit is connected to the first control node, a second control node, and the first shift output terminal, and is configured to perform noise reduction on the first shift output terminal and the first control node in response to a level of the second control node.
10. The shift register unit according to claim 9 , wherein the first inverter is further configured to control the level of the second control node, in response to the first control signal, to obtain the second control signal.
11. The shift register unit according to claim 9 , wherein the first shift register sub-unit further comprises a first inverting circuit, and the first inverting circuit is configured to control the level of the second control node, in response to the first control signal, to obtain the second control signal.
12. The shift register unit according to claim 9 , wherein the second shift register sub-unit comprises a second input circuit, a second output circuit, and a second noise reduction circuit,
wherein the second input circuit is connected to a third control node, and is configured to control a level of the third control node, in response to a second input signal, to obtain the third control signal;
the second output circuit is connected to the third control node and a second shift output terminal, and is configured to output a second shift output signal at the second shift output terminal under control of the third control signal; and
the second noise reduction circuit is connected to the third control node, a fourth control node, and the second shift output terminal, and is configured to perform noise reduction on the second shift output terminal and the third control node in response to a level of the fourth control node.
13. The shift register unit according to claim 12 , wherein the second inverter is configured to control the level of the fourth control node, in response to the third control signal, to obtain the fourth control signal.
14. The shift register unit according to claim 12 , wherein the second shift register sub-unit further comprises a second inverting circuit, and the second inverting circuit is configured to control the level of the fourth control node, in response to the third control signal, to obtain the fourth control signal.
15. A gate drive circuit, comprising a plurality of cascaded shift register units according to claim 1 .
16. The gate drive circuit according to claim 15 , further comprising a first gate drive sub-circuit and a second gate drive sub-circuit, wherein
the first gate drive sub-circuit comprises a plurality of cascaded first shift register sub-units, and the second gate drive sub-circuit comprises a plurality of cascaded second shift register sub-units.
17. The gate drive circuit according to claim 16 ,
wherein except for a first stage of first shift register sub-unit, a first input terminal of each stage of first shift register sub-unit other than the first stage of first shift register sub-unit is connected to a first shift output terminal of a previous stage of first shift register sub-unit; and
except for a first stage of second shift register sub-unit, a second input terminal of each stage of second shift register sub-unit other than the first stage of second shift register sub-unit is connected to a second shift output terminal of a previous stage of second shift register sub-unit.
18. A display device, comprising the gate drive circuit according to claim 15 .
19. A driving method of the OR logic operation circuit in the shift register unit according to claim 1 , comprising:
in a case where the first control signal and the third control signal are both at a first level, outputting the first level of the output signal at the output terminal; and
in a case where at least one of the first control signal and the third control signal is at a second level, outputting the second level of the output signal at the output terminal.