TRANSISTOR WITH WIDE BANDGAP CHANNEL AND NARROW BANDGAP SOURCE/DRAIN
An electronic device comprises a first layer on a buffer layer on a substrate. A source/drain region is deposited on the buffer layer. The first layer comprises a first semiconductor. The source/drain region comprises a second semiconductor. The second semiconductor has a bandgap that is smaller than a bandgap of the first semiconductor. A gate electrode is deposited on the first layer.
1 . An electronic device comprising:
a first layer on a substrate, the first layer comprising a first semiconductor material; and
a source region or a drain region on the substrate, the source region or drain region comprising a second semiconductor material that has a bandgap smaller than a bandgap of the first semiconductor material; and
a gate electrode on the first layer.
2 . The electronic device of claim 1 , wherein the first semiconductor material has a conduction band that has a zero offset relative to the conduction band of the second semiconductor material.
3 . The electronic device of claim 1 , wherein the first semiconductor material has a dopant concentration equal or smaller than 10{circumflex over ( )}16 atoms/cm{circumflex over ( )}3.
4 . The electronic device of claim 1 , wherein each of the first semiconductor material and the second semiconductor material comprises a III-V semiconductor material.
5 . The electronic device of claim 1 , wherein the first semiconductor material comprises gallium arsenide, indium phosphide, gallium phosphide, indium gallium phosphide, aluminum gallium arsenide, gallium arsenide antimonide (GaAs x Sb 1-x ) (where 0≤x≤1), indium gallium arsenide antimonide (In x Ga 1-x As y Sb 1-y ), indium gallium arsenide phosphide (In x Ga 1-x As y P 1-y ), indium gallium arsenide phosphide antimonide In x Ga 1-x P y Sb 1-y (where 0≤x≤0.3, 0≤y≤1), indium aluminum arsenide antimonide In x Al 1-x As y Sb 1-y , indium aluminum arsenide phosphide (In x Al 1-x As y P 1-y ) (where 0.8≤x≤1, 0≤y≤1), or any combination thereof.
6 . The electronic device of claim 1 , wherein the second semiconductor material comprises indium gallium arsenide, indium antimonide, indium gallium antimonide, indium gallium arsenide antimonide (In x Ga 1-x As y Sb 1-y ), indium gallium arsenide phosphide (In x Ga 1-x As y P 1-y ), indium gallium phosphide antimonide (In x Ga 1-x P y Sb 1-y ), indium aluminum arsenide antimonide (In x Al 1-x As y Sb 1-y ), indium aluminum arsenide phosphide (In x Al 1-x As y P 1-y ), where 0≤x≤1, 0≤y≤1, or any combination thereof.
7 . The electronic device of claim 1 , wherein a valence band of the first semiconductor material is offset relative to a valence band of the second semiconductor material by at least 0.4 eV.
8 . The electronic device of claim 1 , further comprising
a gate dielectric on the first layer.
9 . The electronic device of claim 1 , wherein the first layer is a part of a fin, a nanowire, or a nanoribbon.
10 . The electronic device of claim 1 , wherein the source region or drain region is in a recess in the first layer.
11 . A system comprising:
a chip including
an electronic device comprising
a first layer on a substrate; and
a source region or a drain region on the substrate, the first layer comprising a first semiconductor material, the source region or drain region comprising a second semiconductor material that has a bandgap smaller than a bandgap of the first semiconductor material; and
a gate electrode on the first layer.
12 . The system of claim 11 , wherein the first semiconductor material has a conduction band that has a zero offset relative to the conduction band of the second semiconductor material.
13 . The system of claim 11 , wherein each of the first semiconductor material and the second semiconductor material comprises a III-V semiconductor material.
14 . The system of claim 11 , wherein the first semiconductor material comprises gallium arsenide, indium phosphide, gallium phosphide, indium gallium phosphide, aluminum gallium arsenide, gallium arsenide antimonide (GaAs x Sb 1-x ) (where 0≤x≤1), indium gallium arsenide antimonide (In x Ga 1-x As y Sb 1-y ), indium gallium arsenide phosphide (In x Ga 1-x As y P 1-y ), indium gallium arsenide phosphide antimonide In x Ga 1-x P y Sb 1-y (where 0≤x≤0.3, 0≤y≤1), indium aluminum arsenide antimonide In x Al 1-x As y Sb 1-y , indium aluminum arsenide phosphide (In x Al 1-x As y P 1-y ) (where 0.8≤x≤1, 0≤y≤1), or any combination thereof.
15 . The system of claim 11 , wherein the second semiconductor material comprises indium gallium arsenide, indium antimonide, indium gallium antimonide, indium gallium arsenide antimonide (In x Ga 1-x As y Sb 1-y ), indium gallium arsenide phosphide (In x Ga 1-x As y P 1-y ), indium gallium phosphide antimonide (In x Ga 1-x P y Sb 1-y ), indium aluminum arsenide antimonide (In x Al 1-x As y Sb 1-y ), indium aluminum arsenide phosphide (In x Al 1-x As y P 1-y ), where 0≤x≤1, 0≤y≤1, or any combination thereof.
16 . The system of claim 11 , wherein a valence band of the first semiconductor material is offset relative to a valence band of the second semiconductor material by at least 0.4 eV.
17 . The system of claim 11 , further comprising
a gate dielectric on the first layer.
18 . A method to manufacture an electronic device, comprising:
depositing a first layer comprising a first semiconductor material on a substrate;
forming a gate electrode on the first layer;
forming a recess in the first layer;
forming a source region or a drain region in the recess, the source region or drain region comprising a second semiconductor material that has a bandgap greater than a bandgap of the first semiconductor material.
19 . The method of claim 18 , wherein the first semiconductor material has a conduction band that has a zero offset relative to the conduction band of the second semiconductor material.
20 . The method of claim 18 , wherein each of the first semiconductor material and the second semiconductor material comprises a III-V semiconductor material.
21 . The method of claim 18 , wherein the first semiconductor material comprises gallium arsenide, indium phosphide, gallium phosphide, indium gallium phosphide, aluminum gallium arsenide, gallium arsenide antimonide (GaAs x Sb 1-x ) (where 0≤x≤1), indium gallium arsenide antimonide (In x Ga 1-x As y Sb 1-y ), indium gallium arsenide phosphide (In x Ga 1-x As y P 1-y ), indium gallium arsenide phosphide antimonide In x Ga 1-x P y Sb 1-y (where 0≤x≤0.3, 0≤y≤1), indium aluminum arsenide antimonide In x Al 1-x As y Sb 1-y , indium aluminum arsenide phosphide (In x Al 1-x As y P 1-y ) (where 0.8≤x≤1, 0≤y≤1), or any combination thereof.
22 . The method of claim 18 , wherein the second semiconductor material comprises indium gallium arsenide, indium antimonide, indium gallium antimonide, indium gallium arsenide antimonide (In x Ga 1-x As y Sb 1-y ), indium gallium arsenide phosphide (In x Ga 1-x As y P 1-y ), indium gallium phosphide antimonide (In x Ga 1-x P y Sb 1-y ), indium aluminum arsenide antimonide (In x Al 1-x As y Sb 1-y ), indium aluminum arsenide phosphide (In x Al 1-x As y P 1-y ), where 0≤x≤1, 0≤y≤1, or any combination thereof.
23 . The method of claim 18 , wherein a valence band of the first semiconductor material is offset relative to a valence band of the second semiconductor material by at least 0.4 eV.
24 . The method of claim 18 , further comprising:
forming a spacer on the gate electrode; and
etching a portion of the first layer outside the gate electrode to form a recess.
25 . The method of claim 18 , further comprising
removing the gate electrode;
depositing a gate dielectric on the first layer; and
forming a metal gate stack on the gate dielectric.