Space division multiplexing optical coherence tomography using an integrated photonic device

1. An integrated photonic chip suitable for space-division multiplexing optical coherence tomography scanning, the photonic chip comprising:

a substrate;

an optical input port configured to receive an incident singular sampling beam from an external light source;

a plurality of optical output ports configured to transmit a plurality of sampling beams from the chip to a sample to capture scanned images of the sample; and

a multiple branched waveguide structure optically coupling the input port to each of the output ports, the waveguide structure comprising a plurality of interconnected waveguide channels formed in the substrate;

the waveguide channels configured to define a plurality of photonic splitters which divide the incident singular sampling beam received at the input port into the plurality of sampling beams at the output ports;

wherein portions of the waveguide channels between the photonic splitters and output ports have different predetermined lengths to create an optical time delay between each of the plurality of sampling beams;

wherein a difference in the predetermined lengths between the waveguide channels is selected to produce an optical delay shorter than a coherence length of the light source between the plurality of sampling beams so that when images are formed, signals from different physical locations are detected in different frequency bands.

2. The photonic chip according to claim 1 , wherein the photonic splitters are arranged in multiple cascading rows on the substrate, the singular sampling beam being successively divided in each row by the photonic splitters to create an increasingly greater number of sampling beams in each row between the inlet port and the output ports.

3. The photonic chip according to claim 1 , wherein the output ports emit the sampling beams from the photonic chip directly into air to the sample.

4. The photonic chip according to claim 1 , wherein the output ports are arranged to receive a plurality of reflected light signals returned from the sample, the photonic splitters being configured to combine the plurality of reflected light signals into a singular reflected light signal which is emitted from the input port of the photonic chip.

5. The photonic chip according to claim 1 , wherein the plurality of output ports are clustered together on one side of the substrate and evenly spaced apart at a predetermined pitch spacing.

6. The photonic chip according to claim 5 , wherein a difference in length between each adjacent waveguide channel in the photonic chip is the same.

7. The photonic chip according to claim 1 , further comprising an optical fiber coupled to the input port of the photonic chip.

8. The photonic chip according to claim 1 , wherein the substrate is selected from the group consisting of silicon, silicon on insulator, Iridium Phosphide, Lithium Niobate, Silicon Nitride and Gallium Arsenide.

9. The photonic chip according to claim 1 , wherein the sampling beams in the time delay region travel in a path generally perpendicular to a path of the sampling beams in the splitter region.

10. The photonic chip according to claim 1 , wherein the waveguide channels are etched into the substrate.

11. A low loss integrated photonic chip suitable for space-division multiplexing optical coherence tomography scanning, the photonic chip comprising:

a substrate;

an optical input port configured to receive an incident singular sampling beam from an external light source;

a reference light input port configured to receive reference light from an external reference light source;

a plurality of optical output ports configured to transmit a plurality of sampling beams from the chip to a sample to capture scanned images of the sample;

a multiple branched waveguide structure optically coupling the input port to each of the output ports, the waveguide structure comprising a plurality of interconnected waveguide channels formed in the substrate, the waveguide channels defining a splitter region and an interferometer region;

the waveguide channels in the splitter region configured to define a plurality of photonic splitters which divide the incident singular sampling beam received at the input port into the plurality of sampling beams at the output ports;

wherein portions of the waveguide channels between the photonic splitters and output ports have different predetermined lengths to create an optical time delay between each of the plurality of sampling beams;

the waveguide channels in the interferometer region configured to define a plurality of photonic interferometers, the photonic interferometers optically coupled to the waveguide channels in the time delay region and the reference light;

wherein the photonic interferometers are arranged to receive a plurality of reflected light signals returned from the sample, the photonic interferometers being configured and operable to combine the reflected light signals with the reference light to produce a plurality of interference signals which are emitted from interference signal output ports of the photonic chip.

12. The photonic chip according to claim 11 , wherein the photonic splitters are arranged in multiple cascading rows on the substrate, the singular sampling beam being evenly and successively divided in each row by the photonic splitters to create an increasingly greater number of sampling beams in each row between the inlet port and the output ports.

13. The photonic chip according to claims 12 , wherein the photonic interferometers are optically coupled to photonic splitters in a final row of the splitter region.

14. The photonic chip according to claim 13 , wherein the reflected light signals returned from the sample travel through the photonic splitters in the final row to the interferometers and bypass preceding rows of photonic splitters in the splitter region.

15. The photonic chip according to claim 11 , wherein the photonic interferometers are optically coupled to the reference light input port via a plurality of reference light waveguide channels.

16. The photonic chip according to claim 11 , wherein a difference in the predetermined lengths between the waveguide channels is selected to produce an optical delay shorter than a coherence length of the light source between the plurality of sampling beams so that when images are formed, signals from different physical locations are detected in different frequency bands.

17. A method for processing light in a space division multiplexing optical coherence tomography system using a low loss integrated photonic chip, the method comprising:

providing a photonic chip comprising an optical input port, a plurality of optical output ports, and a multiple branched waveguide structure optically coupling the input port to each of the output ports, the waveguide structure comprising a plurality of interconnected waveguide channels formed in the chip;

receiving a singular sample beam from a light source at the input port;

dividing the sample beam into a plurality of sampling beams using a plurality of in-chip photonic splitters defined by the waveguide channels in the splitter region;

creating a time delay between the plurality of sampling beams by varying a length of each waveguide channel after dividing the sampling beam; and

emitting the plurality of sampling beams simultaneously in parallel through the output ports towards a sample to be scanned;

receiving a plurality of reflected light signals returned from the sample at the output ports;

transmitting the reflected light signals to a plurality of interferometers defined by the waveguide channels in an interferometer region of the photonic chip;

combining the reflected light signals with a reference light signal using the plurality of interferometers to generate a plurality of interference signals; and

emitting the interference signals from interference output ports of the photonic chip.