IP Library › Granted Patent US 10,908,973
Granted Patent B2
US 10,908,973 · App. 16/615,408 · Granted Feb 2, 2021

Information processing device

Inventor: Osamu Nasu (Tokyo, JP)
Assignee: MITSUBISHI ELECTRIC CORPORATION
G06F9/542
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Quick Facts
Patent No.
US 10,908,973
App. No.
16/615,408
Granted
Feb 2, 2021
Kind
B2
Abstract

An information processing device includes: a first processing unit that processes data on a real-time operating system that executes processing within a specified time; a second processing unit that processes data on a non-real-time operating system; and a transmission unit that adjusts a data amount of transmission data to be transmitted at a time on the basis of an accumulation amount of transmission data transmitted between the first processing unit and the second processing unit, and transmits the transmission data.

Claims (25)

1. An information processor comprising:

a real-time processor including a first processing circuitry to perform first data processing on industrial data relating to operation of manufacturing equipment on a real-time operating system that executes processing within a specified time; and

a non-real-time processor including a second processing circuitry to perform second data processing on the industrial data on a non-real-time operating system, wherein

the non-real-time processor includes a plurality of second reception circuitries to receive, on the non-real-time operating system, first transmission data transmitted from the real-time processor and output the first transmission data to the second processing circuitry,

the real-time processor includes a first transmission circuitry to adjust, on the real-time operating system, a data amount of the first transmission data, that are data obtained by the first data processing and that are to be transmitted to the second processing circuitry, and transmit the first transmission data to the second reception circuitries,

the first transmission circuitry checks an accumulation amount of the first transmission data for each of the second reception circuitries that are destinations at a predetermined check period, and when a plurality of first transmission data are present, performs, for each of the second reception circuitries, batch processing of transmitting the plurality of first transmission data together, and when a plurality of first transmission data are not present, performs, for each of the second reception circuitries, serial processing of transmitting the first transmission data individually,

when the accumulation amount has exceeded a first threshold, the first transmission circuitry performs a process of transmitting an amount of the first transmission data within the first threshold together to the second reception circuitry for which the accumulation amount has exceeded the first threshold, and

the first threshold is set on the basis of a data amount of first transmission data that can be processed during one check period, the first transmission data being received from the first transmission circuitry by the second reception circuitry.

2. The information processor according to claim 1 , wherein the first transmission circuitry switches between the batch processing and the serial processing on the basis of an elapsed time from previous transmission of the first transmission data.

3. The information processor according to claim 2 , wherein the first transmission circuitry performs the serial processing when the elapsed time has exceeded a predetermined time at occurrence of the first transmission data.

4. The information processor according to claim 1 , wherein the first transmission circuitry includes a data alignment circuitry to perform, when no corresponding data are present among a plurality of kinds of first transmission data, interpolation to compensate for missing data, discarding of the first transmission data, or time shifting of the first transmission data, and align the first transmission data in association with one another, and

the first transmission circuitry adjusts the data amount on the basis of the accumulation amount after the alignment.

5. The information processor according to claim 1 , wherein the real-time processor further includes:

a first management circuitry to control operation timing of the first processing circuitry on the real-time operating system; and

the non-real-time processor includes a second management circuitry to control operation timing of the second processing circuitry on the non-real-time operating system.

6. The information processor according to claim 1 , wherein

the non-real-time processor includes a second transmission circuitry to adjust, on the non-real-time operating system, a data amount of second transmission data to be transmitted from the second processing circuitry to the first processing circuitry, and

the real-time processor includes

a first reception circuitry to receive, on the real-time operating system, the second transmission data from the second transmission circuitry, the number of first reception circuitries being fixed.

7. The information processor according to claim 6 , wherein

the number of first reception circuitries is one, and

the information processor further comprises a reception management circuitry to assign data received by the first reception circuitry to one of the first processing circuitries.

8. The information processor according to claim 7 , wherein

the first processing circuitries each include a data collection processing circuitry to collect data from an external device, and a notification processing circuitry to provide notification of a diagnosis result after processing and diagnosis of the collected data performed by the first processing circuitries or the second processing circuitry, and

the information processor executes a series of processes including processing, on the non-real-time operating system, data collected on the real-time operating system, and thereafter notifying the external device of the diagnosis result by the notification processing circuitry.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2019
From: NASU, OSAMU
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 051072/0610 →
Continuity (1)
Related Publication 20200379825A1 · Dec 3, 2020