Comparison circuit, semiconductor device, electronic component, and electronic device

1. A comparison circuit comprising:

a first input terminal;

a second input terminal;

a first output terminal; and

a differential input circuit comprising a differential pair of a first n-channel transistor and a second n-channel transistor each comprising a gate and a backgate,

wherein the comparison circuit compares a negative voltage and a negative reference voltage and outputs a first output voltage from the first output terminal in response to a comparison result,

wherein the negative voltage is input to the first input terminal,

wherein a positive reference voltage is input to the second input terminal,

wherein the positive reference voltage is determined so that comparison is performed,

wherein a first bias voltage is input to one of the gate and the backgate of the first n-channel transistor,

wherein the first input terminal is electrically connected to the other of the gate and the backgate of the first n-channel transistor,

wherein the second input terminal is electrically connected to one of the gate and the backgate of the second n-channel transistor, and

wherein a second bias voltage is input to the other of the gate and the backgate of the second n-channel transistor.

2. The comparison circuit according to claim 1 ,

wherein the first bias voltage is input to the backgate of the first n-channel transistor, and

wherein a first negative voltage is input to the gate of the first n-channel transistor.

3. The comparison circuit according to claim 1 ,

wherein the positive reference voltage is input to the backgate of the second n-channel transistor, and

wherein the second bias voltage is input to the gate of the second n-channel transistor.

4. The comparison circuit according to claim 1 , wherein the first bias voltage is a high-level-side power supply voltage of the comparison circuit.

5. The comparison circuit according to claim 1 , wherein the second bias voltage is a low-level-side power supply voltage of the comparison circuit.

6. The comparison circuit according to claim 1 , wherein a channel formation region of each of the first n-channel transistor and the second n-channel transistor comprises a metal oxide.

7. The comparison circuit according to claim 1 ,

wherein the comparison circuit is a dynamic comparison circuit, and

wherein the differential input circuit includes a latch circuit electrically connected to the differential pair.

8. A semiconductor device comprising:

a charge pump circuit;

a driver circuit; and

the comparison circuit according to claim 1 ,

wherein an output terminal of the charge pump circuit is electrically connected to the first input terminal of the comparison circuit,

wherein the first output voltage is input from the comparison circuit to the driver circuit, and

wherein the driver circuit generates a clock signal for driving the charge pump circuit in accordance with the first output voltage.

9. The semiconductor device according to claim 8 ,

wherein a plurality of n-channel transistors electrically connected in series is provided in an electric charge transfer path of the charge pump circuit,

wherein the plurality of n-channel transistors each include a backgate electrically connected to a gate, and

wherein a channel formation region of each of the plurality of n-channel transistors includes a metal oxide.

10. A semiconductor device comprising:

first to N voltage output terminals where N is an integer of 2 or more;

a negative voltage generation circuit;

a control circuit;

first to N charge pump circuits;

first to N monitor circuits; and

first to N driver circuits,

wherein the control circuit generates a first clock signal for driving the negative voltage generation circuit,

wherein an output terminal of the negative voltage generation circuit is electrically connected to input terminals of the first to N charge pump circuits,

wherein an output terminal of a j-th charge pump circuit is electrically connected to a j-th voltage output terminal where j is an integer of 1 to N,

wherein a j-th monitor circuit includes a comparison circuit [j],

wherein the comparison circuit [j] is the comparison circuit according to claim 1 ,

wherein the first input terminal of the comparison circuit [j] is electrically connected to the j-th voltage output terminal,

wherein the first output terminal of the comparison circuit [j] is electrically connected to an input terminal of the j-th driver circuit, and

wherein the j-th driver circuit generates a second clock signal for driving the j-th charge pump circuit in accordance with the first clock signal and a first output voltage output from the comparison circuit [j].

11. A semiconductor device comprising:

first to N voltage output terminals where N is an integer of 2 or more;

a negative voltage generation circuit;

a control circuit;

a divider circuit;

first to N charge pump circuits;

first to N monitor circuits; and

first to N driver circuits,

wherein the control circuit generates a first clock signal for driving the negative voltage generation circuit,

wherein the divider circuit divides the first clock signal to generate a second clock signal,

wherein an output terminal of the negative voltage generation circuit is electrically connected to input terminals of the first to N charge pump circuits,

wherein an output terminal of a j-th charge pump circuit is electrically connected to a j-th voltage output terminal where j is an integer of 1 to N,

wherein a j-th monitor circuit includes a comparison circuit [j],

wherein the comparison circuit [j] is the comparison circuit according to claim 7 ,

wherein the first input terminal of the comparison circuit [j] is electrically connected to the j-th voltage output terminal,

wherein the first output terminal of the comparison circuit [j] is electrically connected to an input terminal of the j-th driver circuit, and

wherein the j-th driver circuit generates a third clock signal for driving the j-th charge pump circuit in accordance with the second clock signal and a first output voltage output from the comparison circuit [j].

12. The semiconductor device according to claim 11 ,

wherein the j-th monitor circuit further includes a latch circuit [j] and a circuit [j],

wherein the j-th latch circuit is between the first output terminal of the comparison circuit [j] and the j-th voltage output terminal, and

wherein the circuit [j] inputs a voltage lower than the positive reference voltage to the second input terminal of the comparison circuit [j] in accordance with an output of the j-th latch circuit.

13. The semiconductor device according to claim 11 ,

wherein the j-th monitor circuit further includes a selection circuit [j], and

wherein the selection circuit [j] inputs a low-level-side power supply voltage to the differential input circuit of the comparison circuit [j] in accordance with the first output voltage from the first output terminal of the comparison circuit [j].

14. An electronic component incorporating a chip, wherein the chip includes the semiconductor device according to claim 8 .

15. An electronic device comprising:

the electronic component according to claim 14 , and

at least one of a display portion, a microphone, a speaker, an operation key, and a housing.