Array substrate, manufacturing method thereof, and display device
The present disclosure provides an array substrate, a manufacturing method of the array substrate, and a display device. The array substrate includes a hydrogen ion film formed between an active layer and a source/drain electrode of a low temperature poly-silicon thin film transistor, and a hole is formed in a region of the hydrogen ion film where a metal-oxide-semiconductor thin film transistor is disposed. Based on the hydrogen ion film, the electrical performance and stability of the low temperature poly-silicon thin film transistor are improved. Furthermore, hydrogen elements are not diffused to the region where the metal-oxide-semiconductor thin film transistor is disposed.
1. An array substrate, comprising:
a substrate;
a low temperature poly-silicon thin film transistor and a metal-oxide-semiconductor thin film transistor formed on the substrate; and
a hydrogen ion film formed between an active layer and a source/drain electrode of the low temperature poly-silicon thin film transistor, wherein a hole is formed in a region of the hydrogen ion film where the metal-oxide-semiconductor thin film transistor is disposed;
wherein the array substrate comprises a first insulating layer located between the active layer and a gate electrode of the low temperature poly-silicon thin film transistor, the first insulating layer comprises a first silicon oxide layer and a first silicon nitride layer, and the first silicon nitride layer is patterned to form a first hydrogen ion film of the hydrogen ion film; and
wherein the array substrate comprises a second insulating layer located between the gate electrode and the source/drain electrode of the low temperature poly-silicon thin film transistor, the second insulating layer comprises a second silicon oxide layer and a second silicon nitride layer, and the second silicon nitride layer is patterned to form a second hydrogen ion film of the hydrogen ion film.
2. The array substrate of claim 1 , wherein the second silicon oxide layer is disposed between a gate electrode and an active layer of the metal-oxide-semiconductor thin film transistor.
3. The array substrate of claim 1 , wherein the array substrate comprises a buffer layer formed on the substrate and a third insulating layer located between the gate electrode of the low temperature poly-silicon thin film transistor and the second insulating layer; and
the first silicon oxide layer and the third insulating layer are stacked and disposed between the buffer layer and the gate electrode of the metal-oxide-semiconductor thin film transistor.
4. The array substrate of claim 3 , wherein the active layer of the low temperature poly-silicon thin film transistor is disposed on the buffer layer.
5. The array substrate of claim 3 , wherein a material of the buffer layer is silicon oxide.
6. The array substrate of claim 3 , wherein the array substrate further comprises a storage capacitor; and
a first electrode plate of the storage capacitor and the gate electrode of the low temperature poly-silicon thin film transistor are disposed in the same layer, and a second electrode plate of the storage capacitor and the gate electrode of the metal-oxide-semiconductor thin film transistor are disposed in the same layer.
7. The array substrate of claim 6 , wherein the array substrate further comprises a protection layer; and
the first silicon oxide layer and the first silicon nitride layer are disposed between the buffer layer and the first electrode plate of the storage capacitor, the third insulating layer is disposed between the first electrode plate and the second electrode plate of the storage capacitor, and the second silicon oxide layer and the second silicon nitride layer are disposed between the second electrode plate of the storage capacitor and the protection layer.
8. A manufacturing method of an array substrate, comprising:
providing a substrate; and
manufacturing thin film transistors and a hydrogen ion film;
wherein the thin film transistors comprise a low temperature poly-silicon thin film transistor and a metal-oxide-semiconductor thin film transistor formed on the substrate, the hydrogen ion film is formed between an active layer and a source/drain electrode of the low temperature poly-silicon thin film transistor, and a hole is formed in a region of the hydrogen ion film where the metal-oxide-semiconductor thin film transistor is disposed;
wherein the array substrate comprises a first insulating layer located between the active layer and a gate electrode of the low temperature poly-silicon thin film transistor, the first insulating layer comprises a first silicon oxide layer and a first silicon nitride layer, and the first silicon nitride layer is patterned to form a first hydrogen ion film of the hydrogen ion film; and
wherein the array substrate comprises a second insulating layer located between the gate electrode and the source/drain electrode of the low temperature poly-silicon thin film transistor, the second insulating layer comprises a second silicon oxide layer and a second silicon nitride layer, and the second silicon nitride layer is patterned to form a second hydrogen ion film of the hydrogen ion film.
9. A display device, comprising a display panel, an array substrate of the display panel comprising:
a substrate;
a low temperature poly-silicon thin film transistor and a metal-oxide-semiconductor thin film transistor formed on the substrate; and
a hydrogen ion film formed between an active layer and a source/drain electrode of the low temperature poly-silicon thin film transistor, wherein a hole is formed in a region of the hydrogen ion film where the metal-oxide-semiconductor thin film transistor is disposed;
wherein the array substrate comprises a first insulating layer located between the active layer and a gate electrode of the low temperature poly-silicon thin film transistor, the first insulating layer comprises a first silicon oxide layer and a first silicon nitride layer, and the first silicon nitride layer is patterned to form a first hydrogen ion film of the hydrogen ion film; and
wherein the array substrate comprises a second insulating layer located between the gate electrode and the source/drain electrode of the low temperature poly-silicon thin film transistor, the second insulating layer comprises a second silicon oxide layer and a second silicon nitride layer, and the second silicon nitride layer is patterned to form a second hydrogen ion film of the hydrogen ion film.
10. The display device of claim 9 , wherein the display panel is a liquid crystal display panel or an organic light emitting diode display panel.
11. The display device of claim 9 , wherein the second silicon oxide layer is disposed between a gate electrode and an active layer of the metal-oxide-semiconductor thin film transistor.
12. The display device of claim 9 , wherein the array substrate comprises a buffer layer formed on the substrate and a third insulating layer located between the gate electrode of the low temperature poly-silicon thin film transistor and the second insulating layer; and
the first silicon oxide layer and the third insulating layer are stacked and disposed between the buffer layer and the gate electrode of the metal-oxide-semiconductor thin film transistor.
13. The display device of claim 12 , wherein the active layer of the low temperature poly-silicon thin film transistor is disposed on the buffer layer.
14. The display device of claim 12 , wherein a material of the buffer layer is silicon oxide.
15. The display device of claim 12 , wherein the array substrate further comprises a storage capacitor; and
a first electrode plate of the storage capacitor and the gate electrode of the low temperature poly-silicon thin film transistor are disposed in the same layer, and a second electrode plate of the storage capacitor and the gate electrode of the metal-oxide-semiconductor thin film transistor are disposed in the same layer.
16. The display device of claim 15 , wherein the array substrate further comprises a protection layer; and
the first silicon oxide layer and the first silicon nitride layer are disposed between the buffer layer and the first electrode plate of the storage capacitor, the third insulating layer is disposed between the first electrode plate and the second electrode plate of the storage capacitor, and the second silicon oxide layer and the second silicon nitride layer are disposed between the second electrode plate of the storage capacitor and the protection layer.