IP Library › Granted Patent US 11,443,706
Granted Patent B2
US 11,443,706 · App. 16/617,110 · Granted Sep 13, 2022

Shift register having a compensation circuit, shift register circuit and display device

Inventors: Zhuo Xu (Beijing, CN); Hailong Wu (Beijing, CN); Yajie Bai (Beijing, CN); Haipeng Zhu (Beijing, CN); Min Ran (Beijing, CN); Peng Liang (Beijing, CN); Zhi Zhang (Beijing, CN)
Assignees: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.; Beijing BOE Technology Development Co., Ltd.
G09G3/3611G09G2310/0286G09G2310/08
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Quick Facts
Patent No.
US 11,443,706
App. No.
16/617,110
Granted
Sep 13, 2022
Kind
B2
Abstract

A shift register includes an input circuit, a compensation circuit, an output circuit, a pull-down control circuit, a pull-down circuit, and a reset circuit. During operation of a pixel driving circuit, if a display abnormality occurs in one or more pixels corresponding to the shift register, a compensation signal may be provided by the compensation circuit to a pull-up node according to specific condition of the display abnormality, so as to change a voltage of the pull-up node, and further change a delay time of waveform of the signal passing the switching element in the output circuit connected to the pull-up node.

Claims (105)

1. A shift register, comprising:

an input circuit connected to a pull-up node and configured to provide a signal to the pull-up node;

a compensation circuit connected to the pull-up node and configured to transmit a compensation signal to the pull-up node, the compensation circuit being connected to the input circuit;

an output circuit connected to the pull-up node, an output end, and a first phase clock signal end, and configured to transmit a signal of the first phase clock signal end to the output end in response to a signal of the pull-up node, the output circuit being connected to the input circuit and the compensation circuit;

a pull-down control circuit connected to a first signal end, a pull-down control node, a pull-down node, the pull-up node, and a second signal end, and configured to transmit a signal of the second signal end to the pull-down node and the pull-down control node in response to the signal of the pull-up node, and transmit a signal of the first signal end to the pull-down control node and the pull-down node in response to the signal of the first signal end, the pull-down control circuit being connected to the input circuit;

a pull-down circuit connected to the pull-up node, the pull-down node, the output end and the second signal end, and configured to transmit the signal of the second signal end to the pull-up node and the output end in response to a signal of the pull-down node, the pull-down circuit being connected between the compensation circuit and the output circuit; and

a reset circuit connected to a reset end, the second signal end, and the pull-up node, and configured to transmit the signal of the second signal end to the pull-up node in response to a signal of the reset end, the reset circuit being connected between the input circuit and the pull-down circuit;

wherein the input circuit and the compensation circuit comprise any one of the following circuits:

Circuit I: the input circuit comprises: a first switching element provided with a control end connected to an input end, a first end connected to the first signal end, and a second end connected to the pull-up node; and the compensation circuit comprises: a tenth switching element provided with a control end connected to the input end, a first end connected to a compensation end, and a second end connected to the pull-up node;

Circuit II: the input circuit comprises: a first switching element provided with a control end, a first end connected to an input end, and a second end connected to the pull-up node; and the compensation circuit comprises: a tenth switching element provided with a first end connected to a compensation end and a second end connected to the pull-up node; an eleventh switching element provided with a control end, a first end connected to a second phase clock signal end, and a second end connected to a control end of the tenth switching element; and a twelfth switching element provided with a control end connected to the pull-down node, a first end connected to the second end of the eleventh switching element, and a second end connected to the second signal end; and

Circuit III: the input circuit comprises: a first switching element provided with a control end, a first end connected to an input end, and a second end connected to the pull-up node; and the compensation circuit comprises: a tenth switching element provided with a first end connected to a compensation end; an eleventh switching element provided with a control end, a first end and a second end, wherein the control end and the first end are directly connected to the compensation end, and the second end is connected to a control end of the tenth switching element; a second storage capacitor provided with a first end and a second end, wherein the first end is directly connected to a second end of the tenth switching element, and the second end is connected to the pull-up node; and a twelfth switching element provided with a control end connected to the pull-down node, a first end connected to a second end of the eleventh switching element, and a second end connected to the second signal end.

2. The shift register according to claim 1 , wherein:

the output circuit comprises:

a second switching element provided with a control end connected to the pull-up node, a first end connected to the first phase clock signal end, and a second end connected to the output end; and

a first storage capacitor provided with a first end connected to the pull-up node, and a second end connected to the output end;

the pull-down control circuit comprises:

a third switching element provided with a control end and a first end connected to the first signal end, and a second end connected to the pull-down control node;

a fourth switching element provided with a control end connected to the pull-down control node, a first end connected to the first signal end, and a second end connected to the pull-down node;

a fifth switching element provided with a control end connected to the pull-up node, a first end connected to the pull-down control node, and a second end connected to the second signal end; and

a sixth switching element provided with a control end connected to the pull-up node, a first end connected to the pull-down node, and a second end connected to the second signal end;

the pull-down circuit comprises:

a seventh switching element provided with a control end connected to the pull-down node, a first end connected to the pull-up node, and a second end connected to the second signal end; and

an eighth switching element provided with a control end connected to the pull-down node, a first end connected to the output end, and a second end connected to the second signal end; and

the reset circuit comprises: a ninth switching element provided with a control end connected to the reset end, a first end connected to the pull-up node, and a second end connected to the second signal end.

3. The shift register according to claim 1 , wherein:

the pull-down circuit comprises a first pull-down circuit and a second pull-down circuit, the second signal end comprises a first sub-signal end and a second sub-signal end;

the first pull-down circuit comprises: an eighth switching element, provided with a control end connected to the pull-down node, a first end connected to the output end, and a second end connected to the first sub-signal end, and configured to transmit a signal of the first sub-signal end to the output end in response to the signal of the pull-down node;

the second pull-down circuit comprises: a seventh switching element, provided with a control end connected to the pull-down node, a first end connected to the pull-up node, and a second end connected to the second sub-signal end, and configured to transmit a signal of the second sub-signal end to the pull-up node in response to the signal of the pull-down node; and

the reset circuit is connected to the reset end, the pull-up node, and the second sub-signal end, and configured to transmit the signal of the second sub-signal end to the pull-up node in response to a signal of the reset end.

4. A shift register circuit, comprising:

N cascading shift registers, wherein N is an integer greater than one and any one of the N cascading shift registers comprises:

an input circuit connected to a pull-up node and configured to provide a signal to the pull-up node;

a compensation circuit connected to the pull-up node and configured to transmit a compensation signal to the pull-up node, the compensation circuit being connected to the input circuit;

an output circuit connected to the pull-up node, an output end, and a first phase clock signal end, and configured to transmit a signal of the first phase clock signal end to the output end in response to a signal of the pull-up node, the output circuit being connected to the input circuit and the compensation circuit;

a pull-down control circuit connected to a first signal end, a pull-down control node, a pull-down node, the pull-up node, and a second signal end, and configured to transmit a signal of the second signal end to the pull-down node and the pull-down control node in response to the signal of the pull-up node, and transmit a signal of the first signal end to the pull-down control node and the pull-down node in response to the signal of the first signal end, the pull-down control circuit being connected to the input circuit;

a pull-down circuit connected to the pull-up node, the pull-down node, the output end, and the second signal end, and configured to transmit the signal of the second signal end to the pull-up node and the output end in response to a signal of the pull-down node, the pull-down circuit being connected between the compensation circuit and the output circuit; and

a reset circuit connected to a reset end, the second signal end, and the pull-up node, and configured to transmit the signal of the second signal end to the pull-up node in response to a signal of the reset end, the reset circuit being connected between the input circuit and the pull-down circuit,

wherein, according to a cascade relationship of the cascading shift registers, the second signal ends of the cascading shift registers at a first stage to an N-th stage are sequentially connected to N-th signal terminal to first signal terminal.

5. The shift register circuit according to claim 4 , wherein:

the pull-down circuit of the shift register circuit comprises a first pull-down circuit and a second pull-down circuit, the second signal end comprising a first sub-signal end and a second sub-signal end;

the first pull-down circuit comprises: an eighth switching element provided with a control end connected to the pull-down node, a first end connected to the output end, and a second end connected to the first sub-signal end, and configured to transmit a signal of the first sub-signal end to the output end in response to the signal of the pull-down node;

the second pull-down circuit comprises: a seventh switching element provided with a control end connected to the pull-down node, a first end connected to the pull-up node, and a second end connected to the second signal end, and configured to transmit a signal of the second sub-signal end to the pull-up node in response to the signal of the pull-down node; and

the reset circuit of the shift register circuit is connected to the reset end, the pull-up node, and the second sub-signal end, and is configured to transmit the signal of the second sub-signal end to the pull-up node in response to a signal of the reset end.

6. The shift register circuit according to claim 5 , wherein:

the signal of the first sub-signal end comprises a first signal to an N-th signal received from the first signal terminal to the N-th signal terminal;

according to the cascade relationship of the cascading shift registers, the first sub-signal ends of the cascading shift registers at the first stage to the N-th stage are sequentially connected to the N-th signal terminal to the first signal terminal; and

according to the cascade relationship of the cascading shift registers, the second sub-signal ends of the cascading shift registers at the first stage to the N-th stage are connected to the first signal terminal.

7. The shift register circuit according to claim 5 , wherein:

the signal of the first sub-signal end comprises a first signal to an (N+1)-th signal received from the first signal terminal to an (N+1)-th signal terminal;

according to the cascade relationship of the cascading shift registers, the first sub-signal ends of the cascading shift registers at the first stage to the N-th stage are sequentially connected to the (N+1)-th signal terminal to a second signal terminal; and

according to the cascade relationship of the cascading shift registers, the second sub-signal ends of the cascading shift registers at the first stage to the N-th stage are sequentially connected to the N-th signal terminal to the first signal terminal.

8. The shift register circuit according to claim 5 , wherein:

the input circuit comprises: a first switching element provided with a control end, a first end connected to an input end, and a second end connected to the pull-up node; and

the compensation circuit comprises: a tenth switching element provided with a control end connected to the input end, a first end connected to a compensation end, and a second end connected to the pull-up node.

9. The shift register circuit according to claim 5 , wherein:

the input circuit comprises: a first switching element provided with a control end connected to an input end, a first end connected to the first signal end, and a second end connected to the pull-up node; and

the compensation circuit comprises: a tenth switching element provided with a control end connected to the input end, a first end connected to a compensation end, and a second end connected to the pull-up node.

10. The shift register circuit according to claim 5 , wherein:

the input circuit comprises: a first switching element provided with a control end, a first end connected to an input end, and a second end connected to the pull-up node; and

the compensation circuit comprises:

a tenth switching element provided with a first end connected to a compensation end, and a second end connected to the pull-up node;

an eleventh switching element provided with a control end and a first end connected to a second phase clock signal end, and a second end connected to a control end of the tenth switching element; and

a twelfth switching element provided with a control end connected to the pull-down node, a first end connected to the second end of the eleventh switching element, and a second end connected to the second signal end.

11. The shift register circuit according to claim 5 , wherein:

the input circuit comprises: a first switching element provided with a control end, a first end connected to an input end, and a second end connected to the pull-up node; and

the compensation circuit comprises:

a tenth switching element provided with a first end connected to a compensation end;

an eleventh switching element provided with a control end and a first end connected to the compensation end, and a second end connected to a control end of the tenth switching element;

a second storage capacitor provided with a first end connected to a second end of the tenth switching element, and a second end connected to the pull-up node; and

a twelfth switching element provided with a control end connected to the pull-down node, a first end connected to a second end of the eleventh switching element, and a second end connected to the second signal end.

12. The shift register circuit according to claim 5 , wherein:

the output circuit comprises:

a second switching element provided with a control end connected to the pull-up node, a first end connected to the first phase clock signal end, and a second end connected to the output end; and

a first storage capacitor provided with a first end connected to the pull-up node, and a second end connected to the output end;

the pull-down control circuit comprises:

a third switching element provided with a control end, a first end connected to the first signal end, and a second end connected to the pull-down control node;

a fourth switching element provided with a control end connected to the pull-down control node, a first end connected to the first signal end, and a second end connected to the pull-down node;

a fifth switching element provided with a control end connected to the pull-up node, a first end connected to the pull-down control node, and a second end connected to the second signal end; and

a sixth switching element, provided with a control end connected to the pull-up node, a first end connected to the pull-down node, and a second end connected to the second signal end;

the pull-down circuit comprises:

a seventh switching element provided with a control end connected to the pull-down node, a first end connected to the pull-up node, and a second end connected to the second signal end; and

an eighth switching element provided with a control end connected to the pull-down node, a first end connected to the output end, and a second end connected to the second signal end; and

the reset circuit comprises: a ninth switching element provided with a control end connected to the reset end, a first end connected to the pull-up node, and a second end connected to the second signal end.

13. A display device, comprising:

a shift register circuit comprising N cascading shift registers, wherein N is an integer greater than one and any one of the N cascading shift registers comprises:

an input circuit connected to a pull-up node and configured to provide a signal to the pull-up node;

a compensation circuit connected to the pull-up node and configured to transmit a compensation signal to the pull-up node, the compensation circuit being connected to the input circuit;

an output circuit connected to the pull-up node, an output end, and a first phase clock signal end, and configured to transmit a signal of the first phase clock signal end to the output end in response to a signal of the pull-up node, the output circuit being connected to the input circuit and the compensation circuit;

a pull-down control circuit connected to a first signal end, a pull-down control node, a pull-down node, the pull-up node, and a second signal end, and configured to transmit a signal of the second signal end to the pull-down node and the pull-down control node in response to the signal of the pull-up node, and transmit a signal of the first signal end to the pull-down control node and the pull-down node in response to the signal of the first signal end, the pull-down control circuit being connected to the input circuit;

a pull-down circuit connected to the pull-up node, the pull-down node, the output end, and the second signal end, and configured to transmit the signal of the second signal end to the pull-up node and the output end in response to a signal of the pull-down node, the pull-down circuit being connected between the compensation circuit and the output circuit; and

a reset circuit connected to a reset end, the second signal end, and the pull-up node, and configured to transmit the signal of the second signal end to the pull-up node in response to a signal of the reset end, the reset circuit being connected between the input circuit and the pull-down circuit,

wherein, according to a cascade relationship of the cascading shift registers, the second signal ends of the cascading shift registers at a first stage to an N-th stage are sequentially connected to N-th signal terminal to first signal terminal.

14. The display device according to claim 13 , wherein:

the pull-down circuit of the shift register circuit comprises a first pull-down circuit and a second pull-down circuit, the second signal end comprises a first sub-signal end and a second sub-signal end;

the first pull-down circuit comprises: an eighth switching element provided with a control end connected to the pull-down node, a first end connected to the output end, and a second end connected to the first sub-signal end, and configured to transmit a signal of the first sub-signal end to the output end in response to the signal of the pull-down node;

the second pull-down circuit comprises: a seventh switching element provided with a control end connected to the pull-down node, a first end connected to the pull-up node, and a second end connected to the second signal end, and configured to transmit a signal of the second sub-signal end to the pull-up node in response to the signal of the pull-down node; and

the reset circuit of the shift register circuit is connected to the reset end, the pull-up node, and the second sub-signal end, and configured to transmit the signal of the second sub-signal end to the pull-up node in response to a signal of the reset end.

15. The display device according to claim 14 , wherein:

the signal of the first sub-signal end comprises a first signal to an N-th signal received from the first signal terminal to the N-th signal terminal;

according to the cascade relationship of the cascading shift registers, the first sub-signal ends of the cascading shift registers at the first stage to the N-th stage are sequentially connected to the N-th signal terminal to the first signal terminal; and

according to the cascade relationship of the cascading shift registers, the second sub-signal ends of the cascading shift registers at the first stage to the N-th stage are connected to the first signal terminal.

16. The display device according to claim 14 , wherein:

the signal of the first sub-signal end comprises a first signal to an (N+1)-th signal received from the first signal terminal to an (N+1)-th signal terminal;

according to the cascade relationship of the cascading shift registers, the first sub-signal ends of the cascading shift registers at the first stage to the N-th stage are sequentially connected to the a (N+1)-th signal terminal to a second signal terminal; and

according to the cascade relationship of the cascading shift registers, the second sub-signal ends of the cascading shift registers at the first stage to the N-th stage are sequentially connected to the N-th signal terminal to the first signal terminal.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2022
From: BOE TECHNOLOGY GROUP CO., LTD.
To: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
Reel/Frame 060653/0894 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2020
From: XU, ZHUO; WU, HAILONG; BAI, YAJIE; ZHU, HAIPENG; RAN, MIN; LIANG, PENG; ZHANG, ZHI
To: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.; BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 053174/0822 →
Priority Claims (1)
CN 201810602101.4 · Jun 12, 2018 · national
Continuity (1)
Related Publication 20220005428A1 · Jan 6, 2022
Cited By (1)
US 12,217,696