Method for calibrating capacitor voltage coefficient of high-precision successive approximation analog-to-digital converter
The present disclosure relates to the field of semiconductor integrated circuits, and to a method for calibrating a capacitor voltage coefficient of a high-precision successive approximation analog-to-digital converter (SAR ADC). The method includes: calibrating a voltage coefficient; obtaining a sampled charged charge according to a capacitance model with the voltage coefficient; according to an INL value obtained by testing, first verifying whether a maximum value of INL occurs in the place shown in Equation 3, then obtaining two very close second-order capacitor voltage coefficients according to Equation 4, and taking an average value thereof as a second-order capacitor voltage coefficient; and then calibrating the second-order capacitor voltage coefficient in a digital domain. In the present disclosure, a capacitor voltage coefficient can be extracted based on INL and the capacitor voltage coefficient is calibrated at a digital backend without adding an analog calibration circuit, thereby improving conversion accuracy of the ADC.
1. A method for calibrating a capacitor voltage coefficient of a high-precision successive approximation analog-to-digital converter (SAR ADC), comprising:
calibrating a voltage coefficient, a capacitance model with the voltage coefficient is shown in Equation 1:
C=C 0 *(1+α1* V+α 2* V 2 + . . . ) (1)
wherein C is an actual value of a capacitor, C 0 is a nominal value of the capacitor when a voltage difference between two ends of the capacitor is 0, α1 is a first-order capacitor voltage coefficient, V is a voltage difference between the two ends of the capacitor, and α2 is a second-order capacitor voltage coefficient; sampling to obtain a charged charge:
Q=C 0 *( V+ 0.5*α1* V 2 +⅓*α2* V 3 + . . . ) (2)
wherein the ADC uses a differential structure, a related term 0.5*α1*V 2 of the first-order voltage coefficient is canceled during sampling; if a high-order capacitor voltage coefficient is omitted, a related term ⅓*α2*V 3 of the second-order capacitor voltage coefficient becomes a dominant factor of nonlinearity, and the second-order capacitor voltage coefficient is extracted and calibrated according to an integral nonlinearity (INL) curve of the ADC; and the shape of the INL curve is determined by the second-order voltage coefficient, and a digital code for generating maximum INL is shown in Equation 3:
D out1=min( D out)/√{square root over (3)}
D out2=max( D out)/√{square root over (3)} (3)
wherein Dout is an output digital code of the ADC, a value at a minimum value of INL in a negative value range of Dout is set to Dout1, a value at a maximum value of INL in a positive value range of Dout is set to Dout2, min(Dout) represents a minimum value of Dout, and max(Dout) represents a maximum value of Dout; and
a maximum INL value is shown in Equation 4:
max( INL )=2*α21*(max( D out)) 3 /3 2.5
min( INL )=2*α22*(min( D out)) 3 /3 2.5 (4)
wherein max(INL) represents the maximum value of INL, min(INL) represents the minimum value of INL, α21 represents a second-order voltage coefficient value derived from the maximum value of INL, and α22 represents a second-order voltage coefficient value derived from the minimum value of INL;
according to an INL value obtained by testing, first verifying whether a maximum value of INL occurs in the place shown in Equation 3, then obtaining two very close second-order capacitor voltage coefficients according to Equation 4, and taking an average value thereof as a second-order capacitor voltage coefficient, as shown in Equation 5:
α2
=
α21
+
α22
2
;
(
5
)
and
then calibrating the second-order capacitor voltage coefficient in a digital domain, a calibration formula is shown in Equation 6:
D out_ cal=D out−⅓*α2 *D out 3 (6)
wherein Dout_cal is a calibrated ADC digital output code.